DS1677E Maxim Integrated Products, DS1677E Datasheet - Page 8

• Manufacturer Part Number: DS1677E
• Description: IC CTRLR SYSTEM PORT 20-TSSOP
• Manufacturer: Maxim Integrated Products
• Type: Portable System Controllerr

Specifications of DS1677E

• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: 3-Wire Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Memory Size: -

MICROPROCESSOR MONITOR
The DS1677 monitors three vital conditions for a microprocessor: power supply, software execution, and
external override.
First, a precision temperature-compensated reference and comparator circuit monitors the status of V
When an out-of-tolerance condition occurs, an internal power-fail signal is generated which forces the
V
250ms (typical) to allow the power supply and microprocessor to stabilize. Note however that if the
kept in an active state for 250ms plus the startup time of the oscillator.
The second monitoring function is push-button reset control. The DS1677 provides for a push–button
switch to be connected to the
monitors the
switch by pulling the
to monitor the
rising edge. Upon detecting release, the DS1677 will force the
The third microprocessor monitoring function provided by the DS1677 is a watchdog timer. The
watchdog timer function forces
predetermined time period. The time period is set by the Time Delay (TD) bits in the Watchdog Register.
The time delay can be set to 250ms, 500ms, or 1000ms (see Figure 4). If TD0 and TD1 are both set to
zero, the watchdog timer is disabled. When enabled, the watchdog timer starts timing out from the set
time period as soon as
1000 ms time delay. If a high-to-low transition occurs on the
timer is reset and begins to time out again. If the watchdog timer is allowed to time out, then the
signal is driven to the active state for 250ms (typical). The
address signals, data signals, and/or control signals. To guarantee that the watchdog timer does not time
out, a high-to-low transition must occur at or less than the minimum period.
WATCHDOG TIMEOUT CONTROL Figure 4
WATCHDOG REGISTER
WATCHDOG REGISTER
RST
EOSC
CC
BIT 7
TD1
returns to an in-tolerance condition upon power-up, the reset signal is kept in the active state for
0
pin to the active state thus warning a processor-based system of impending power failure. When
0
0
1
1
bit is set to a logic 1 (to disable the oscillator during battery-backup mode), the
RST
RST
BIT 6
0
signal for a low going edge. If an edge is detected, the DS1677 will debounce the
TD0
line. If the line is still low, the DS1677 will continue to monitor the line looking for a
0
1
0
1
RST
RST
line low. After the internal 250ms timer has expired, the DS1677 will continue
is inactive. The default setting is for the watchdog timer to be enabled with
BIT 5
RST
WATCHDOG DISABLED
250ms
500ms
1000ms
0
RST
WATCHDOG TIMEOUT
output pin. When the DS1677 is not in a reset cycle, it continuously
to the active state when the
BIT 4
0
8 of 18
BIT 3
0
ST
ST
RST
input can be derived from microprocessor
input pin prior to time out, the watchdog
ST
line low and hold it low for 250ms.
BIT 2
input is not stimulated within the
0
BIT 1
TD1
RST
signal will be
BIT 0
TD0
RST
CC
.