M48T59Y-70PC1 STMicroelectronics, M48T59Y-70PC1 Datasheet - Page 11

• Manufacturer Part Number: M48T59Y-70PC1
• Description: IC TIMEKPR NVRAM 64KBIT 5V 28-DI
• Manufacturer: STMicroelectronics
• Series: Timekeeper®r
• Type: Clock/Calendar/NVSRAMr

Specifications of M48T59Y-70PC1

• Memory Size: 64K (8K x 8)
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 28-DIP Module (600 mil), 28-EDIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2862-5

2.3
Note:
Table 4.
1. Valid for ambient operating temperature: T
2. C
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
Data retention mode
With valid V
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself when V
become high impedance, and all inputs are treated as “don't care.”
A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below V
user can be assured the memory will be in a write protected state, provided the V
is not less than t
reach into the deselect window during the time the device is sampling V
decoupling of the power supply lines is recommended.
When V
preserves data and powers the clock. The internal button cell will maintain data in the
M48T59/Y/V for an accumulated period of at least 7 years when V
system power returns and V
supply is switched to external V
(max).
For more information on Battery Storage Life refer to the Application Note AN1012.
t
t
WHQX
WLQZ
Symbol
(except where noted).
t
t
t
t
t
t
t
t
t
t
t
t
t
WLWH
WHDX
WHAX
DVWH
AVWH
L
AVWL
EHAX
EHDX
ELEH
DVEH
AVEH
AVAV
AVEL
= 5pF (see
(2)(3)
(2)(3)
CC
drops below V
CC
Write mode AC characteristics
WRITE cycle time
Address valid to WRITE enable low
Address valid to chip enable low
WRITE enable pulse width
Chip enable low to chip enable high
WRITE enable high to address transition
Chip enable high to address transition
Input valid to WRITE enable high
Input valid to chip enable high
WRITE enable high to input transition
Chip enable high to input transition
WRITE enable low to output Hi-Z
Address valid to WRITE enable high
Address valid to chip enable high
WRITE enable high to output transition
Figure 13 on page
applied, the M48T59/Y/V operates as a conventional BYTEWIDE™ static
F
. The M48T59/Y/V may respond to transient noise spikes on V
CC
SO
falls within the V
, the control circuit switches power to the internal battery which
CC
Parameter
22).
rises above V
CC
. Deselect continues for t
A
= 0 to 70°C; V
(1)
PFD
SO
(max), V
, the battery is disconnected and the power
CC
= 4.5 to 5.5 V, 4.75 to 5.5 V, or 3.0 to 3.6 V
PFD
rec
(min) window. All outputs
after V
Min
70
50
55
30
30
60
60
0
0
0
0
5
5
5
M48T59/Y/V
CC
CC
is less than V
–70
CC
reaches V
. Therefore,
PFD
Max
25
(min), the
CC
CC
PFD
that
SO
fall time
. As
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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