M48T212V-85MH1F STMicroelectronics, M48T212V-85MH1F Datasheet
M48T212V-85MH1F
Specifications of M48T212V-85MH1F
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M48T212V-85MH1F Summary of contents
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... Watchdog timer ■ Automatic power-fail chip deselect and WRITE protection ■ WRITE protect voltage (V = Power-fail deselect voltage): PFD – M48T212V 3.0 to 3.6V CC 2.7V V 3.0V PFD ■ Packaging includes a 44-lead SOIC and ® SNAPHAT top (to be ordered separately) ■ ...
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Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Description The M48T212V is a self-contained device that includes a real-time clock (RTC), programmable alarms, a watchdog timer, and two external chip enable outputs which provide control four (two in parallel) external low-power static RAMs. Access to all TIMEKEEPER byte-wide SRAM. The 16 TIMEKEEPER Registers offer Century, Year, Month, Date, Day, Hour, Minute, Second, Calibration, Alarm, Watchdog, and Flags ...
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Table 1. Signal names A0-A3 DQ0-DQ7 RSTIN1 RSTIN2 RST WDI CON E2 CON IRQ/FT V CCSW V OUT 6/35 Address inputs Data inputs/outputs Reset 1 input Reset 2 input ...
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... Figure 2. SOIC connections RSTIN1 RSTIN2 RST WDI E2 CON DQ0 DQ1 DQ2 OUT CCSW 4 41 IRQ/ M48T212V CON 17 28 DQ7 18 27 DQ6 19 26 DQ5 20 25 DQ4 21 24 DQ3 AI03020 7/35 ...
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... If the second chip enable pin (E2) is unused, it should be tied to V Note: See description in Power Supply Decoupling and Undershoot Protection. 8/35 A0-A18 A0-A3 V CCSW OUT CON Note CON WDI RSTIN1 RSTIN2 RST DQ0-DQ7 IRQ/ M48T212V to external SRAM should be as short as possible. . OUT MOTOROLA MTD20P06HDL A0-Axx (3) CMOS SRAM E A0-Axx (3) CMOS SRAM E AI03046 ...
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... Byte 1h contains century information. Byte 0h contains additional flag information pertaining to the watchdog timer, alarm and battery status. The M48T212V also has its own Power-Fail Detect circuit. This control circuitry constantly monitors the supply voltage for an out of tolerance condition. When V the circuit write protects the TIMEKEEPER data security in the midst of unpredictable system operation ...
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Table 2. Operating modes Mode V CC Deselect WRITE 3.0V to 3.6V READ READ Deselect (min) SO PFD (1) Deselect See Table 14 on page 28 for details. Note ...
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... CON 2.2 Read mode The M48T212V executes a READ cycle whenever W (WRITE Enable) is high and E (Chip Enable) is low. The unique address specified by the address inputs (A3-A0) defines which one of the on-chip TIMEKEEPER presented to the M48T212V is in the range of 0h-Fh, one of the on-board TIMEKEEPER ...
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... Write mode The M48T212V is in the WRITE Mode whenever W (WRITE Enable) and E (Chip Enable) are in a low state after the address inputs are stable. The start of a WRITE is referenced from the latter occurring falling edge WRITE is terminated by the earlier rising edge ...
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Figure 6. Write cycle timing: RTC control signal waveforms ADDRESS tAVEL E G tAVWL W tEHQZ DATA OUT DQ0-DQ7 VALID Note assumed high. WRITE WRITE tAVAV tAVAV tAVEH tAVWH tELEH tEHAX tWHAX tEHDX tWLWH tDVEH tDVWH DATA IN ...
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... On power up, when V protection continues for 200ms (max) by inhibiting E1 The RST signal also remains active during this time (see Note: Most low power SRAMs on the market today can be used with the M48T212V ® TIMEKEEPER SUPERVISOR. There are, however some criteria which should be used in ...
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... The system level requirements will determine the choice of which value to use. The data retention current value of the SRAMs can then be added to the I M48T212V to determine the total current requirements for data retention. The available battery capacity for the SNAPHAT determine the amount of data retention available (see For a further more detailed review of lifetime calculations, please see Application Note AN1012 ...
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... Clock operation 3.1 TIMEKEEPER The M48T212V offers 16 internal registers which contain TIMEKEEPER Watchdog, Flag, and Control data. These registers are memory locations which contain external (user accessible) and internal copies of the data (usually referred to as BiPORT TIMEKEEPER cells). The external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy ...
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... The STOP Bit is located at Bit D7 within the Seconds Register (9h). Setting '1' stops the oscillator. When reset to a '0,' the M48T212V oscillator starts within one second. Note not necessary to set the WRITE Bit when setting or resetting the FREQUENCY TEST Bit (FT) or the STOP Bit (ST) ...
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Table 7. TIMEKEEPER Address WDS BMB4 BMB3 6h AFE 5h RPT4 RPT5 4h RPT3 3h RPT2 2h RPT1 1h 0h WDF Keys: S ...
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... The ABE and AFE Bits are reset during power-up, therefore an alarm generated during power-up will only set AF. The user can read the Flag Register at system boot-up to determine if an alarm was generated while the M48T212V was in the deselect mode during power-up. Figure 8 on page 20 Figure 7 ...
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... Note: Accuracy of timer is within ± the selected resolution. If the processor does not reset the timer within the specified period, the M48T212V sets the WDF (Watchdog Flag) and generates a watchdog interrupt or a microprocessor reset. WDF is reset by reading the Flags Register (Address 0h). ...
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... If the RST output is fed back into either of the RSTIN inputs (for a microprocessor with a bi- directional reset) then a 1k 3.9 Reset inputs (RSTIN1 & RSTIN2) The M48T212V provides two independent inputs which can generate an output reset. The duration and function of these resets is identical to a reset generated by a power cycle. Table 9 and ...
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... L 3.10 Calibrating the clock The M48T212V is driven by a quartz controlled oscillator with a nominal frequency of 32,768 Hz. The devices are tested not to exceed ±35 ppm (parts per million) oscillator frequency error at 25°C, which equates to about ±1.53 minutes per month (see When the Calibration circuit is properly employed, accuracy improves to better than +1/–2 ppm at 25° ...
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... Battery low warning The M48T212V automatically performs battery voltage monitoring upon power-up and at factory-programmed time intervals of approximately 24 hours. The Battery Low (BL) Bit, Bit D4 of Flags Register 0h, will be asserted if the battery voltage is found to be less than approximately 2.5V. The BL Bit will remain asserted until completion of battery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval ...
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Additionally battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique. 3.12 Initial power-on defaults ...
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... In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on V one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, STMicroelectronics recommends connecting a Schottky diode from V Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount ...
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... Caution: Negative undershoots below –0.3V are not allowed on any pin while in the battery back-up mode. Caution: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets. 26/35 Parameter ® SNAPHAT SOIC M48T212V Value Unit °C – °C –55 to 125 °C 260 °C – ...
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... Input pulse voltages Input and output timing ref. voltages Note: Output High Z is defined as the point where data is no longer driven. Figure 13. AC testing load circuit Note: Excluding open-drain output pins; 50pF for M48T212V. 1. DQ0-DQ7 2. E1 and E2 CON CON conditions. Designers should check that the operating ...
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... Table 13. Capacitance Symbol Parameter C Input capacitance IN (3) C Input/output capacitance OUT 1. Effective capacitance measured with power supply at 3.3V (M48T212V); sampled only, not 100% tested 25° 1MHz. 3. Outputs deselected. Table 14. DC characteristics Sym Parameter (2) I Input leakage current LI (3) I Output leakage current LO I Supply current ...
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... RB SS PFD t V (max) to RST high rec PFD 1. Valid for ambient operating temperature: T tFB DON'T CARE HIGH-Z (1) Parameter (min) V fall time CC fall time M48T212V CC (max) V rise time CC rise time 70° 3.0 to 3.6V (except where noted tRB trec VALID VALID AI02638 Min ...
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Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner ...
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Figure 16. SH – 4-pin SNAPHAT housing for 48 mAh battery & crystal, package outline Note: Drawing is not to scale. Table 17. SH – 4-pin SNAPHAT housing for 48 mAh battery & crystal, pack. mech. data Symb Typ A ...
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Figure 17. SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package outline Note: Drawing is not to scale. Table 18. SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, pack. mech. data Symb ...
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... Table 19. Ordering information scheme Example: Device type M48T Supply and write protect voltage 212V = V = 3.0 to 3.6V; 2.7V CC Speed –85 = 85ns (for M48T212V) Package ( SOH44 Temperature range 70°C Shipping method E = Lead-free package (ECOPACK F = Lead-free package (ECOPACK 1. The SOIC package (SOH44) requires the SNAPHAT the part number “ ...
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Revision history Table 21. Document revision history Date Revision Oct-1999 01-Mar-2000 21-Apr-2000 10-Nov-2000 30-May-2001 10-Sep-2001 13-May-2002 16-Jul-2002 27-Mar-2003 31-Mar-2004 05-Nov-2007 34/35 1.0 First Issue 2.0 Document layout changed; default Values table added 3.0 From Preliminary Data to datasheet 3.1 ...
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... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...