X1226S8 Intersil, X1226S8 Datasheet - Page 12

• Manufacturer Part Number: X1226S8
• Description: IC RTC CLNDR OUTFREQ 4K EE 8SOIC
• Manufacturer: Intersil
• Type: Clock/Calendar/EEPROMr

Specifications of X1226S8

• Memory Size: 4K (512 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Figure 6. Slave Address, Word Address, and Data Bytes (64 Byte pages)
Write Operations
Byte Write
For a write operation, the device requires the Slave
Address Byte and the Word Address Bytes. This gives
the master access to any one of the words in the array
or CCR. (Note: Prior to writing to the CCR, the master
must write a 02h, then 06h to the status register in two
preceding operations to enable the write operation.
See “Writing to the Clock/Control Registers.” Upon
receipt of each address byte, the X1226 responds with
Figure 7. Byte Write Sequence
Figure 8. Writing 30 bytes to a 64-byte memory page starting at address 40.
Array
CCR
7 Bytes
Signals from
the Master
SDA Bus
Signals From
The Slave
Address
= 6
A7
1
1
D7
0
12
Device Identifier
A6
0
1
D6
0
Address Pointer
Ends Here
Addr = 7
S
a
t
r
t
A5
D5
1
0
0
1
Address
Slave
1
A4
D4
0
1
0
1
1
0
A
C
K
A3
D3
0 0 0 0 0 0 0
1
0
Address 1
X1226
Word
A2
D2
1
0
an acknowledge. After receiving both address bytes
the X1226 awaits the eight bits of data. After receiving
the 8 data bits, the X1226 again responds with an
acknowledge. The master then terminates the transfer
by generating a stop condition. The X1226 then
begins an internal write cycle of the data to the nonvol-
atile memory. During the internal write cycle, the
device inputs are disabled, so the device will not
respond to any requests from the master. The SDA out-
put is at high impedance. See Figure 7.
Address
A
C
K
40
A1
D1
Address 0
1
0
Word
R/W
A8
A0
D0
A
C
K
Slave Address Byte
Byte 0
Word Address 1
Byte 1
Word Address 0
Byte 2
Data Byte
Byte 3
23 Bytes
Data
Address
A
C
K
63
S
o
p
t
May 8, 2006
FN8098.3