DS1742-70 Maxim Integrated Products, DS1742-70 Datasheet - Page 3

• Manufacturer Part Number: DS1742-70
• Description: IC RTC RAM Y2K 5V 70NS 24-EDIP
• Manufacturer: Maxim Integrated Products
• Type: Clock/Calendar/NVSRAM/Y2Kr

Specifications of DS1742-70

• Memory Size: 16K (2K x 8)
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 24-DIP (600 mil) Module
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

CLOCK OPERATIONS—READING THE CLOCK
While the double-buffered register structure reduces the chance of reading incorrect data, internal updates
to the DS1742 clock registers should be halted before clock data is read to prevent reading of data in
transition. However, halting the internal clock register updating process does not affect clock accuracy.
Updating is halted when a 1 is written into the read bit, bit 6 of the century register, see Table 2. As long
as a 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the count, that
is day, date, and time that was current at the moment the halt command was issued. However, the internal
clock registers of the double-buffered system continue to update so that the clock accuracy is not affected
by the access of data. All of the DS1742 registers are updated simultaneously after the internal clock
register updating process has been re-enabled. Updating is within a second after the read bit is written to
0. The READ bit must be a zero for a minimum of 500ms to ensure the external registers will be updated.
Figure 1. DS1742 BLOCK DIAGRAM
Table 1. TRUTH TABLE
V
V
SO
CC
V
< V
< V
CC
V
> V
CC
CC
SO
< V
< V
PF
PF
PF
V
V
V
V
CE
X
X
IH
IL
IL
IL
V
V
OE
X
X
X
X
IH
IL
WE
V
V
V
X
X
X
IL
IH
IH
Deselect
Deselect
Deselect
MODE
Write
Read
Read
3 of 15
Data Out
High-Z
Data In
High-Z
High-Z
High-Z
DQ
Data Retention Mode
CMOS Standby
POWER
Standby
Active
Active
Active