LTC2442CG#PBF Linear Technology, LTC2442CG#PBF Datasheet - Page 16

• Manufacturer Part Number: LTC2442CG#PBF
• Description: IC ADC 24BIT 4CH 36-SSOP
• Manufacturer: Linear Technology

Specifications of LTC2442CG#PBF

• Number Of Bits: 24
• Sampling Rate (per Second): 8k
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 50mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 36-SSOP (0.200", 5.30mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIO S I FOR ATIO
External Serial Clock, Single Cycle Operation
(SPI/MICROWIRE Compatible)
This timing mode uses an external serial clock to shift out
the conversion result and a CS signal to monitor and control
the state of the conversion cycle, see Figure 4.
The serial clock mode is selected by the EXT pin. To select
the external serial clock mode, EXT must be tied low.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin.
EOC = 1 (BUSY = 1) while a conversion is in progress
and EOC = 0 (BUSY = 0) if the device is in the sleep state.
Independent of CS, the device automatically enters the
sleep state once the conversion is complete.
LTC2442
16
(EXTERNAL)
BUSY
SDO
SCK
SDI
CS
CONVERSION
TEST EOC
U
TEST EOC
U
SLEEP
Hi-Z
1
BIT 31
EOC
Figure 4. External Serial Clock, Single Cycle Operation
1
W
2
BIT 30
“0”
0
0.1V TO V
3
REFERENCE
BIT 29
ANALOG
SIG
INPUTS
EN
VOLTAGE
0.1µF
0.1µF
1µF
4.5V TO 5.5V
4
U
BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21
CC
MSB
SGL
29
30
31
28
12
13
11
17
18
10
6
7
8
9
5
ODD
V
REF
REF
CH0
CH1
CH2
CH3
COM
OUTA
–INA
ADCINA
OUTB
–INB
ADCINB
CC
+
–
LTC2442
6
0
MUXOUTA
MUXOUTB
7
BUSY
+INA
+INB
GND
When the device is in the sleep state (EOC = 0), its conver-
sion result is held in an internal static shift register. The
device remains in the sleep state until the fi rst rising edge
of SCK is seen. Data is shifted out the SDO pin on each
falling edge of SCK. This enables external circuitry to latch
the output on the rising edge of SCK. EOC can be latched
on the fi rst rising edge of SCK and the last bit of the con-
version result can be latched on the 32nd rising edge of
SCK. On the 32nd falling edge of SCK, the device begins
a new conversion. SDO goes HIGH (EOC = 1) and BUSY
goes HIGH indicating a conversion is in progress.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z
and BUSY monitored for the completion of a conversion.
SDO
SCK
EXT
SDI
CS
0
V
F
V
O
+
–
V
21
27
25
26
19
24
4, 5, 32
CC
8
DATA OUTPUT
33
36
35
34
TO 15V
3
1
2
A0
–15V TO GND
1µF
9
OSR3
4-WIRE
SPI INTERFACE
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
10
OSR2
(SIMULTANEOUS 50Hz/60Hz
REJECTION AT 6.9Hz OUTPUT RATE
11
OSR1
12
BIT 20 BIT 19
OSR0 TWOX
13
14
32
BIT 0
LSB
CONVERSION
Hi-Z
2442 F04
2442f