CS5351-KZZ Cirrus Logic Inc, CS5351-KZZ Datasheet - Page 18

• Manufacturer Part Number: CS5351-KZZ
• Description: IC ADC AUD 108DB 204KHZ 24-TSSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS5351-KZZ

• Package / Case: 24-TSSOP
• Number Of Converters: 2
• Number Of Bits: 24
• Sampling Rate (per Second): 204k
• Data Interface: Serial
• Power Dissipation (max): 243mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Conversion Rate: 192 KSPS
• Resolution: 24 bit
• Number Of Adc Inputs: 2
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 10 C
• Mounting Style: SMD/SMT
• Power Consumption: 135 mW
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1781 - EVALUATION BOARD FOR CS5351
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1085-5

18
4.4
4.5
Analog Connections
The analog modulator samples the input at 6.144 MHz. The digital filter will reject signals within the stop-
band of the filter. However, there is no rejection for input signals which are (n
band frequency, where n=0,1,2,...Refer to
noise energy at 6.144 MHz, in addition to providing the optimum source impedance for the modulators. The
use of capacitors which have a large voltage coefficient (such as general purpose ceramics) must be avoid-
ed since these can degrade signal linearity.
High-Pass Filter and DC Offset Calibration
The operational amplifiers in the input circuitry driving the CS5351 may generate a small DC offset into the
A/D converter. The CS5351 includes a high pass filter after the decimator to remove any DC offset which
could result in recording a DC level, possibly yielding "clicks" when switching between devices in a multi-
channel system.
The high pass filter continuously subtracts a measure of the DC offset from the output of the decimation
filter. If the HPF pin is taken high during normal operation, the current value of the DC offset register is frozen
and this DC offset will continue to be subtracted from the conversion result. This feature makes it possible
to perform a system DC offset calibration by:
Running the CS5351 with the high pass filter enabled until the filter settles. See the Digital Filter Character-
istics for filter settling time.
Disabling the high pass filter and freezing the stored DC offset.
A system calibration performed in this way will eliminate offsets anywhere in the signal path between the
calibration point and the CS5351.
100 kΩ
100 kΩ
1 μF
Figure 24. CS5351 Recommended Analog Input Buffer
1 μF
100 kΩ
100 kΩ
+
-
+
-
Figure 24
470 pF
470 pF
C0G
C0G
which shows the suggested filter that will attenuate any
634 Ω
634 Ω
91 Ω
91 Ω
-
+
1 μF
2700 pF
0.01 μF
2700 pF
C0G
C0G
×
6.144 MHz) the digital pass-
AINL
AINR
VQ1
VQ3
VQ2
CS5351
CS5351
DS565F2