CS5351-KZZ Cirrus Logic Inc, CS5351-KZZ Datasheet - Page 3

• Manufacturer Part Number: CS5351-KZZ
• Description: IC ADC AUD 108DB 204KHZ 24-TSSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS5351-KZZ

• Package / Case: 24-TSSOP
• Number Of Converters: 2
• Number Of Bits: 24
• Sampling Rate (per Second): 204k
• Data Interface: Serial
• Power Dissipation (max): 243mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Conversion Rate: 192 KSPS
• Resolution: 24 bit
• Number Of Adc Inputs: 2
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 10 C
• Mounting Style: SMD/SMT
• Power Consumption: 135 mW
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1781 - EVALUATION BOARD FOR CS5351
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1085-5

DS565F2
LIST OF FIGURES
LIST OF TABLES
Figure 1. Single-Speed Mode Stopband Rejection ..................................................................................... 8
Figure 2. Single-Speed Mode Transition Band ........................................................................................... 8
Figure 3. Single-Speed Mode Transition Band (Detail) ............................................................................... 8
Figure 4. Single-Speed Mode Passband Ripple ......................................................................................... 8
Figure 5. Double-Speed Mode Stopband Rejection .................................................................................... 8
Figure 6. Double-Speed Mode Transition Band .......................................................................................... 8
Figure 7. Double-Speed Mode Transition Band (Detail) ............................................................................. 9
Figure 8. Double-Speed Mode Passband Ripple ........................................................................................ 9
Figure 9. Quad-Speed Mode Stopband Rejection ...................................................................................... 9
Figure 10. Quad-Speed Mode Transition Band .......................................................................................... 9
Figure 11. Quad-Speed Mode Transition Band (Detail) .............................................................................. 9
Figure 12. Quad-Speed Mode Passband Ripple ........................................................................................ 9
Figure 13. Master Mode, Left-Justified SAI ............................................................................................... 12
Figure 14. Slave Mode, Left-Justified SAI ................................................................................................. 12
Figure 15. Master Mode, I²S SAI ............................................................................................................... 12
Figure 16. Slave Mode, I²S SAI ................................................................................................................. 12
Figure 17. OVFL Output Timing ................................................................................................................ 12
Figure 18. Left-Justified Serial Audio Interface ......................................................................................... 13
Figure 19. I²S Serial Audio Interface ......................................................................................................... 13
Figure 20. OVFL Output Timing, I²S Format ............................................................................................. 13
Figure 21. OVFL Output Timing, Left-Justified Format ............................................................................. 13
Figure 22. Typical Connection Diagram .................................................................................................... 15
Figure 23. CS5351 Master Mode Clocking ............................................................................................... 17
Figure 24. CS5351 Recommended Analog Input Buffer ........................................................................... 18
Table 1. CS5351 Mode Control ................................................................................................................. 16
Table 2. CS5351 Slave Mode Clock Ratios .............................................................................................. 16
Table 3. CS5351 Common Master Clock Frequencies ............................................................................. 17
CS5351
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