CS5534-ASZ Cirrus Logic Inc, CS5534-ASZ Datasheet - Page 43

• Manufacturer Part Number: CS5534-ASZ
• Description: IC ADC 24BIT 4CH W/LNA 20SSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS5534-ASZ

• Number Of Converters: 1
• Package / Case: 24-SSOP
• Number Of Bits: 24
• Sampling Rate (per Second): 3.84k
• Data Interface: Serial
• Power Dissipation (max): 45mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 4
• Architecture: Delta-Sigma
• Conversion Rate: 6.25 SPs to 3840 SPs
• Resolution: 24 bit
• Input Type: Voltage
• Interface Type: Serial (3-Wire)
• Voltage Reference: 2.5 V
• Maximum Power Dissipation: 500 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1016 - EVAL BOARD FOR CS5534
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1115-5

2.12. Getting Started
This A/D converter has several features. From a
software programmer’s prospective, what should
be done first? To begin, a 4.9152 MHz or
4.096 MHz crystal takes approximately 20 ms to
start. To accommodate for this, it is recommended
that a software delay of approximately 20 ms start
the processor’s ADC initialization code. Next,
since the CS5531/32/33/34 do not provide a power-
on-reset function, the user must first initialize the
ADC to a known state. This is accomplished by re-
setting the ADC’s serial port with the Serial Port
Initialization sequence. This sequence resets the se-
rial port to the command mode and is accomplished
by transmitting 15 SYNC1 command bytes (0xFF
hexadecimal), followed by one SYNC0 command
(0xFE hexadecimal). Once the serial port of the
ADC is in the command mode, the user must reset
all the internal logic by performing a system reset
sequence (see 2.3.2 System Reset Sequence). The
next action is to initialize the voltage reference
mode. The voltage reference select (VRS) bit in the
configuration register must be set based upon the
DS289F5
magnitude of the reference voltage between the
VREF+ and the VREF- pins.
After this, the channel-setup registers (CSRs) should
be initialized, as these registers determine how cali-
brations and conversions will be performed. Once
the CSRs are initialized, the user has three options in
calibrating the ADC: 1) don’t calibrate and use the
default settings; 2) perform self or system calibra-
tions; or 3) upload previously saved calibration re-
sults to the offset and gain registers. At this point,
the ADC is ready to perform conversions.
2.13. PCB Layout
For optimal performance, the CS5531/32/33/34
should be placed entirely over an analog ground
plane. All grounded pins on the ADC, including the
DGND pin, should be connected to the analog
ground plane that runs beneath the chip. In a split-
plane system, place the analog-digital plane split
immediately adjacent to the digital portion of the
chip.
CS5531/32/33/34-AS
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