AD9430BSVZ-210 Analog Devices Inc, AD9430BSVZ-210 Datasheet - Page 28

• Manufacturer Part Number: AD9430BSVZ-210
• Description: IC ADC 12BIT 210MSPS 3.3V100TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9430BSVZ-210

• Data Interface: Parallel
• Number Of Bits: 12
• Sampling Rate (per Second): 210M
• Number Of Converters: 1
• Power Dissipation (max): 1.7mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad
• Resolution (bits): 12bit
• Sampling Rate: 210MSPS
• Input Channel Type: Differential
• Supply Voltage Range - Digital: 3V To 3.6V
• Supply Current: 390mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9430
EVALUATION BOARD, CMOS MODE
The AD9430 evaluation board offers an easy way to test the
AD9430 in CMOS mode. It requires a clock source, an analog
input signal, and a 3.3 V power supply. The clock source is
buffered on the board to provide the clocks for the ADC,
latches, and data ready signals. The digital outputs and output
clocks are available at two 40-pin connectors, P3 and P23. The
PCB interfaces directly with ADI standard dual-channel data
capture board (HSC-ADC-EVAL-DC) which, together with
ADI ADC Analyzer software, allows for quick ADC evaluation.
The board has several different modes of operation and is
shipped in the following configurations:
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POWER CONNECTOR
Power is supplied to the board via a detachable 12-lead power
strip (three 4-pin blocks). AVDD, DRVDD, and VDL are the
minimum required power connections.
Table 10. Power Connector, CMOS Mode
AVDD 3.3 V
DRVDD 3.3 V
VDL 3.3 V
EXT_VREF
VCLK/V_XTAL
VAMP
ANALOG INPUTS
The evaluation board accepts a 1.3 V p-p analog input signal
centered at ground at SMB connector J4. This signal is
terminated to ground through 50 Ω by R16. The input can be
alternatively terminated at the transformer T1 secondary by
R13 and R14. T1 is a wideband RF transformer providing the
single-ended-to-differential conversion, allowing the ADC to be
driven differentially and minimizing even-order harmonics.
An optional second transformer, T2, can be placed following
T1 if desired. This provides some performance advantage
(~1 dB to 2 dB) for high analog input frequencies (>100 MHz).
If T2 is placed, two shorting traces at the pads need to be cut.
The analog signal is low-pass filtered by R41, C12 and R42, and
C13 at the ADC input.
Offset binary
Internal voltage reference
CMOS parallel timing
Full-scale adjust = low
Analog supply for ADC (350 mA)
Output supply for ADC (28 mA)
Supply for support logic and DAC (350 mA)
Optional external reference input
Supply for clock buffer/optional CRYSTAL
Supply for optional amp
Rev. E | Page 28 of 44
GAIN
Full scale is set at E17, E18, and E19. Connecting E17 to E18
sets S5 low, full scale = 1.5 V differential; connecting E17 to E19
sets S5 high, full scale = 0.75 V differential.
ENCODE
The ENCODE clock is terminated to ground through 50 Ω at
SMB Connector J5. The input is ac coupled to a high speed
differential receiver (LVEL16) that provides the required
low jitter, fast edge rates needed for optimum performance.
J5 input should be >0.5 V p-p. Power to the EL16 is set at
Jumper E47. Connecting E47 to E45 powers the buffer from
AVDD; connecting E47 to E46 powers the buffer from
VCLK/V_XTAL.
VOLTAGE REFERENCE
The AD9430 has an internal 1.23 V voltage reference. The ADC
uses the internal reference as the default when jumpers E24 to
E27 and E25 to E26 are left open. The full scale can be increased
by placing optional Resistor R3. The required value varies with
the process and needs to be tuned for the specific application.
Full scale can similarly be reduced by placing R4; tuning is
required here as well. An external reference can be used by
shorting the SENSE pin to 3.3 V (place Jumper E26 to E25).
The E27 to E24 jumper connects the ADC VREF pin to the
EXT_VREF pin at the power connector.
DATA FORMAT SELECT
Data format select sets the output data format of the ADC.
Setting DFS (E1 to E2) low sets the output format to be offset
binary; setting DFS high (E1 to E3) sets the output to twos
complement.
I/P TIMING SELECT
Output timing is set at E11, E12 and E13. E12 to E11 sets S4
low for parallel output timing mode. E11 to E13 sets S4 high
for interleaved timing mode.
TIMING CONTROLS
Flexibility in latch clocking and output timing is accomplished
by allowing for clock inversion at the timing controls section of
the PCB. Each buffered clock is buffered by an XOR and can be
inverted by moving the appropriate jumper for that clock.