KAD2708L-35Q68 Intersil, KAD2708L-35Q68 Datasheet - Page 14

• Manufacturer Part Number: KAD2708L-35Q68
• Description: IC ADC 8BIT 350MSPS SGL 68-QFN
• Manufacturer: Intersil
• Series: FemtoCharge™r

Specifications of KAD2708L-35Q68

• Number Of Bits: 8
• Sampling Rate (per Second): 350M
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 365mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-VQFN Exposed Pad, 68-HVQFN, 68-SQFN, 68-DHVQFN
• For Use With: KDC2708LEVAL - DAUGHTER CARD FOR KAD2708
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Equivalent Circuits
IN P
IN N
10 0
9 5
9 0
8 5
8 0
7 5
7 0
6 5
6 0
5 5
5 0
1
AV D D 3
A VD D3
FIGURE 27. SNR vs CLOCK JITTER
tj=1 00 ps
FIGURE 28. ANALOG INPUTS
2pF
1 0
In put Fr equen cy - MH z
Φ
F 1
Φ
F 1
tj=10 p s
14
Φ
Φ
F 2
F 2
tj=1 ps
tj=0.1 ps
1 00
DATA
DATA
C sam p
C sam p
0.3pF
0.3pF
FIGURE 30. LVDS OUTPUTS
OVDD
1 0 Bits
14 Bits
12 Bits
Pipeline
Pipeline
C harge
C harge
To
To
KAD2708L
1 00 0
DATA
DATA
OVDD
Any internal aperture jitter combines with the input clock jitter
in a root-sum-square fashion, since they are not statistically
correlated, and this determines the total jitter in the system.
The total jitter, combined with other noise sources, then
determines the achievable SNR.
Digital Outputs
Data is output on a parallel bus with LVDS-compatible
drivers.
The output format (Binary or Two’s Complement) is selected
via the 2SC pin as shown in Table 3.
CLKN
CLKP
AVDD (or unconnected)
OVDD
AVDD2
AVDD2
2SC PIN
AVSS
D[7:0]P
D[7:0]N
TABLE 3. 2SC PIN SETTINGS
FIGURE 29. CLOCK INPUTS
Two’s Complement
AVDD2
MODE
Binary
April 14, 2011
Generation
To Clock
FN6813.1