KAD2710L-17Q68 Intersil, KAD2710L-17Q68 Datasheet
KAD2710L-17Q68
Specifications of KAD2710L-17Q68
Related parts for KAD2710L-17Q68
KAD2710L-17Q68 Summary of contents
Page 1
... Features IN include an over-range indicator and a selectable divide-by-2 input clock divider. The KAD2710L is one member of a pin-compatible family offering 8 and 10-bit ADCs with sample rates from 105MSPS to 350MSPS and LVDS-compatible or LVCMOS outputs (Table 1). This family of products is available in 68-pin RoHS-compliant QFN packages with exposed paddle. Performance is specified over the full industrial temperature range (-40° ...
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... KAD2710L-27Q68 KAD2710L-21Q68 KAD2710L-17Q68 KAD2710L-10Q68 NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 ...
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... Functional Description ................................................. 11 Reset .......................................................................... 11 Voltage Reference...................................................... 11 Analog Input ............................................................... 11 Clock Input ................................................................. 12 Jitter............................................................................ 12 Digital Outputs ............................................................ 13 Equivalent Circuits........................................................ 13 Layout Considerations ................................................. 14 Split Ground and Power Planes ................................. 14 Clock Input Considerations......................................... 14 Bypass and Filtering ................................................... 14 LVDS Outputs ............................................................ 14 Unused Inputs ............................................................ 14 Definitions...................................................................... 14 Package Outline Drawing ............................................. 15 L68.10x10B ................................................................ 15 3 KAD2710L FN6818.0 December 5, 2008 ...
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... Nyquist 53.5 55.6 53.5 56.2 = 430MHz 55.2 = 10MHz 55.3 = Nyquist 52.5 55.2 52.5 56.0 = 430MHz 54.4 = 275MSPS, 210MSPS, SAMPLE KAD2710L-21 KAD2710L-17 KAD2710L-10 1.5 1.6 1.4 1.5 1.6 1.4 210 198 860 860 1.8 1.9 1.7 1.8 1.9 1.7 3.3 3 ...
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... AVDD3 AVSS VIN = OVDD IH I VIN = OVSS CDI R CDI V CCI 275MSPS, 210MSPS, SAMPLE KAD2710L-21 KAD2710L-17 KAD2710L-10 9.0 9.1 9.0 8.4 9.0 8.4 8 62.6 60 -12 - 600 600 MIN TYP MAX 0.8*AVDD3 0.2*AVDD3 0 10 -90 -65 -30 0.8*AVDD3 0.2*AVDD3 100 -10 0.8*OVDD2 0.2*OVDD2 0 10 ...
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... Industry-standard protection techniques have been utilized in the design of this product. However, reasonable care must be taken in the storage and handling of ESD sensitive products. Contact Intersil for the specific ESD sensitivity rating of this product. 6 KAD2710L Sample PID ...
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... Exposed Paddle 7 KAD2710L NAME AVDD2 1.8V Analog Supply AVSS Analog Supply Return VREF Reference Voltage Out/In VREFSEL Reference Voltage Select (0:Int 1:Ext) VCM Common-Mode Voltage Output AVDD3 3.3V Analog Supply ...
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... AVDD3 6 AVSS 7 INP 8 INN 9 AVSS 10 DNC 11 DNC 12 DNC 13 AVDD2 14 AVDD3 15 AVDD3 16 CLKDIV 17 8 KAD2710L KAD2710C (68 LD QFN) TOP VIEW KAD2710L 68 QFN Top View Not to Scale FIGURE 2. PIN CONFIGURATION 51 D6P 50 D6N 49 D5P 48 D5N 47 D4P 46 D4N 45 OVSS 44 OVDD2 43 CLKOUTP 42 CLKOUTN 41 OVDD2 40 D3P 39 D3N ...
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... A (dBFS) IN FIGURE 5. SNR AND SFDR SFDR SNR 100 150 (MSPS) SAMPLE S FIGURE 7. SNR AND SFDR KAD2710L AVDD2 = OVDD2 = 1.8V, AVDD3 = 3.3V -0.5dBFS unless noted. IN -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 0 IN -40 -45 -50 -55 HD2 -60 -65 -70 -75 -80 -85 -90 -10 ...
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... CODE FIGURE 11. INTEGRAL NONLINEARITY vs OUTPUT CODE 0 -20 -40 -60 -80 -100 -120 FREQUENCY (MHz) FIGURE 13. OUTPUT SPECTRUM KAD2710L AVDD2 = OVDD2 = 1.8V, AVDD3 = 3.3V -0.5dBFS unless noted. (Continued 0.75 0.5 0.25 0 -0.25 -0.5 -0. 200 250 300 FIGURE 10. DIFFERENTIAL NONLINEARITY vs OUTPUT CODE ...
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... FREQUENCY (MHz) FIGURE 17. TWO-TONE SPECTRUM SFDR 65 60 SNR 55 50 -40 - Ambient Temperature deg.C FIGURE 19. SNR vs TEMPERATURE 11 KAD2710L AVDD2 = OVDD2 = 1.8V, AVDD3 = 3.3V -0.5dBFS unless noted. (Continued Ain = -0.50dBFS SNR = 56.0dBFS -20 SFD R = 63.6dBc -40 SINAD = 55.1dBc HD2 = -67.8dBc -60 HD3 = - 63.6dBc -80 -100 -120 0 80 ...
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... KAD2710L chips.One option in the latter configuration is to use one KAD2710L's internally generated reference as the external reference voltage for the other chips in the system. Additionally, an externally provided reference can be changed from the nominal value to adjust the full-scale input voltage within a limited range ...
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... KAD2710L Ω VCM 25O Use of the clock divider is optional. The KAD2710L's ADC 0.1µF requires a clock with 50% duty cycle for optimum performance. If such a clock is not available, one option is to generate twice the desired sampling rate and use the KAD2710L's divide-by-2 setting. This frequency divider uses the rising edge of the clock, so 50% clock duty cycle is assured ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 14 KAD2710L Digital Outputs Data is output on a parallel bus with LVDS-compatible drivers. ...
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... Differential Non-Linearity (DNL) is the deviation of any code width from an ideal 1 LSB step. 15 KAD2710L Effective Number of Bits (ENOB alternate method of specifying Signal to Noise-and-Distortion Ratio (SINAD calculated as: ENOB = (SINAD - 1.76)/6.02 Gain Error is the ratio of the difference between the voltages that cause the lowest and highest code transitions to the full-scale voltage (less 2 LSB) ...
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... Package Outline Drawing L68.10x10B 68 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 11/08 PIN 1 10.00 INDEX AREA 6 10.00 TOP VIEW 8.00 Sq 9.65 Sq 7.70 Sq TYPICAL RECOMMENDED LAND PATTERN 16 KAD2710L Exp. DAP 7.70 Sq. 35 (4X) 0.15 34 68X 0.55 BOTTOM VIEW 0.90 Max 64X 0.50 68X 0. ...