MAX191BCNG+ Maxim Integrated Products, MAX191BCNG+ Datasheet - Page 16

• Manufacturer Part Number: MAX191BCNG+
• Description: IC ADC 12BIT 100KSPS W/REF 24DIP
• Manufacturer: Maxim Integrated Products

Specifications of MAX191BCNG+

• Number Of Bits: 12
• Sampling Rate (per Second): 100k
• Data Interface: MICROWIRE™, Parallel, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 1.07W
• Voltage Supply Source: Dual ±
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 24-DIP (0.300", 7.62mm)
• Number Of Adc Inputs: 1
• Architecture: SAR
• Conversion Rate: 100 KSPs
• Resolution: 12 bit
• Input Type: Voltage
• Interface Type: Serial
• Voltage Reference: Internal 4.096 V or External
• Supply Voltage (max): 5 V
• Maximum Power Dissipation: 1067 mW
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

where t
quired at the serial data input to the µP. For example,
Motorola’s MC68HC11A8 data book specifies a 100ns
minimum data-setup time. Using the worst case for a
military grade part of t
Characteristics ) and substituting in the above equation
indicates a maximum SCLK frequency of 1.3MHz.
Figure 13 shows interface connections to the MAX191
for common serial-interface standards.
The MAX191 is compatible with SPI, QSPI and
MICROWIRE serial-interface standards. When using SPI
or QSPI, two modes are available to interface with the
MAX191. You can set CPOL = 0 and CPHA = 0 (Figure
14a), or set CPOL = 1 and CPHA = 1 (Figure 14b). When
using CPOL = 0 and CPHA = 0, the conversion begins
on the first falling edge of SCLK following CS going low.
Data is available from DOUT on the rising edge of SCLK,
and transitions on the falling edge. Two consecutive
1-byte reads are required to get the full 12 bits from the
ADC. The first byte contains the following, in this order: a
leading unknown bit (DOUT will still be high-impedance
on the first bit), a 0, and the six MSBs. The second byte
contains the remaining six LSBs and two trailing 0s.
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
Figure 14. SPI/MICROWIRE Serial-Interface Timing
16
DOUT
DOUT
SCLK
a. CPOL = 0, CPHA = 0
SCLK
b. CPOL = 1, CPHA = 1
CS
CS
______________________________________________________________________________________
HIGH-Z
HIGH-Z
Using the MAX191 with SPI, QSPI and
su
f
(M) is the minimum data-setup time re-
SCLK
SPI and MICROWIRE (CPOL=0, CPHA=0)
(MAX) = (1/2) x 1/ (t
LEADING
LEADING
MICROWIRE Serial Interfaces
ZERO
ZERO
MSB
MSB
22
D10
D10
1ST BYTE READ
= 280ns (see Timing
su
D9
D9
(M) + t
D8
D8
22
)
D7
D7
D6
D6
D5
D5
Setting CPOL = 1 and CPHA = 1 starts the clock high
during a read instruction. The MAX191 will shift out a
leading 0 followed by the 12 data bits and three trailing
0s (Figure 14b).
Unlike SPI, which requires two 1-byte reads to acquire
the 12 bits of data from the ADC, QSPI allows the mini-
mum number of clock cycles required to clock in the
data (Figure 15).
Figure 13d shows the pin connections to interface the
MAX191 to the TMS320. Since the MAX191 makes data
available on the rising edge of SCLK and the TMS320
shifts data in on the falling edge of CLKR, use CLKX of the
DSP to drive SCLK, and CLKX to drive the DSP’s CLKR
input. The inverter’s propagation delay also provides more
data-setup time at the DSP. For example, with no inverter
delay, and using t
available setup time before the SCLK transition is:
setup time = 1/ (2 x f
This still exceeds the 13ns minimum DR setup time before
the CLKR goes low (tsu(DR)), however, a generic 74HC04
provides an additional 20ns setup time (see Figure 13d).
Figure 16 shows the DSP interface timing characteris-
tics. The DSP begins clocking data in on the falling
edge of CLKR after the falling edge of SSTRB.
D4
D4
SPI (CPOL=1, CPHA=1)
D3
D3
2ND BYTE READ
D2
D2
SCLK
22
= 280ns and f
D1
D1
) - t
22
= 1/ (2 x 1.6E6) - 280ns = 32ns
LSB
LSB
TMS320 Serial Interface
SCLK
= 1.6MHz, the
HIGH-Z
HIGH-Z
QSPI