MAX11044ETN+ Maxim Integrated Products, MAX11044ETN+ Datasheet - Page 13

ADC 16BIT SAMPLING 4CH 56-TQFN

MAX11044ETN+

Manufacturer Part Number
MAX11044ETN+
Description
ADC 16BIT SAMPLING 4CH 56-TQFN
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of MAX11044ETN+

Number Of Bits
16
Sampling Rate (per Second)
250k
Data Interface
Parallel
Number Of Converters
4
Power Dissipation (max)
2.22W
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
56-WQFN Exposed Pad, 56-HWQFN
Number Of Adc Inputs
4
Architecture
SAR
Conversion Rate
250 KSPs
Resolution
16 bit
Input Type
Voltage
Interface Type
Parallel
Snr
92.3 dB
Voltage Reference
Internal 4.096 V
Supply Voltage (max)
5.25 V
Supply Voltage (min)
2.7 V, 4.75 V
Maximum Power Dissipation
2222 mW
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Input Voltage
5 V
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
27, 33, 40, 48,
31, 34, 47, 50
MAX11044
(TQFP-EP)
26, 55
54
37
39
42
44
41
61
62
63
64
______________________________________________________________________________________
27, 33, 40, 48,
MAX11045
(TQFP-EP)
26, 55
31, 50
PIN
54
34
37
39
42
41
44
47
61
62
63
64
27, 33, 40, 48,
MAX11046
(TQFP-EP)
26, 55
54
31
34
37
39
41
42
44
47
50
61
62
63
64
Simultaneous-Sampling ADCs
RDC_SENSE
4-/6-/8-Channel, 16-/14-Bit,
NAME
REFIO
DB15
RDC
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
WR
I.C.
CS
RD
EP
Reference Buffer Sense Feedback. Connect to RDC
plane.
Refer ence Buffer D ecoup l i ng . C onnect al l RD C outp uts
tog ether . Byp ass to AG N D w i th at l east an 80µF total
cap aci tance. S ee the Layout, Gr ound i ng , and Byp assi ng
secti on.
Channel 0 Analog Input
Channel 1 Analog Input
Channel 2 Analog Input
Channel 3 Analog Input
External Reference Input/Internal Reference Output.
Place a 0.1µF capacitor from REFIO to AGND.
Channel 4 Analog Input
Channel 5 Analog Input
Channel 6 Analog Input
Channel 7 Analog Input
Active-Low Write Input. Drive WR low to write to the
ADC. Configuration registers are loaded on the rising
edge of WR.
Active-Low Chip-Select Input. Drive CS low when
reading from or writing to the ADC.
Active-Low Read Input. Drive RD low to read from the
ADC. Each rising edge of RD advances the channel
output on the data bus.
16-Bit Parallel Data Bus Digital Output Bit 15
Internally Connected. Connect to AGND.
E xp osed P ad . Inter nal l y connected to AG N D . C onnect to
a l ar g e g r ound p l ane to m axi m i ze ther m al p er for m ance.
N ot i ntend ed as an el ectr i cal connecti on p oi nt.
Pin Description (continued)
FUNCTION
13

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