LTC2220IUP-1#PBF Linear Technology, LTC2220IUP-1#PBF Datasheet - Page 24

• Manufacturer Part Number: LTC2220IUP-1#PBF
• Description: IC ADC 12BIT 185MSPS 64-QFN
• Manufacturer: Linear Technology

Specifications of LTC2220IUP-1#PBF

• Number Of Bits: 12
• Sampling Rate (per Second): 185M
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 1.18W
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-WFQFN, Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LTC2220/LTC2221
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2220/LTC2221 should drive a
minimal capacitive load to avoid possible interaction be-
tween the digital outputs and sensitive input circuitry. The
output should be buffered with a device such as an
ALVCH16373 CMOS latch. For full speed operation the
capacitive load should be kept under 10pF.
Lower OV
from the digital outputs.
Digital Output Buffers (LVDS Mode)
Figure 13b shows an equivalent circuit for a differential
output pair in the LVDS output mode. A 3.5mA current is
steered from OUT
±350mV differential voltage across the 100Ω termination
resistor at the LVDS receiver. A feedback loop regulates
the common mode output voltage to 1.25V. For proper
operation each LVDS output pair needs an external 100Ω
termination resistor, even if the signal is not used (such as
OF
PC board traces for each LVDS output pair should be
routed close together. To minimize clock skew all LVDS PC
board traces should have about the same length.
APPLICATIO S I FOR ATIO
24
+
/OF
LTC2220/LTC2221
–
or CLKOUT
DD
Figure 13b. Digital Output in LVDS Mode
–
+
D
D
voltages will also help reduce interference
1.25V
+
to OUT
U
+
10k
/CLKOUT
OV
DD
OGND
10k
U
3.5mA
–
or vice versa which creates a
–
). To minimize noise the
22201 F13b
D
D
W
OUT
OUT
100Ω
+
–
RECEIVER
U
LVDS
Data Format
The LTC2220/LTC2221 parallel digital output can be se-
lected for offset binary or 2’s complement format. The
format is selected with the MODE pin. Connecting MODE
to GND or 1/3V
Connecting MODE to 2/3V
ment output format. An external resistor divider can be
used to set the 1/3V
shows the logic states for the MODE pin.
Table 3. MODE Pin Function
MODE Pin
0
1/3V
2/3V
V
Overflow Bit
An overflow output bit indicates when the converter is
overranged or underranged. In CMOS mode, a logic high
on the OFA pin indicates an overflow or underflow on the
A data bus, while a logic high on the OFB pin indicates an
overflow or underflow on the B data bus. In LVDS mode,
a differential logic high on the OF
overflow or underflow.
Output Clock
The ADC has a delayed version of the ENC
as a digital output, CLKOUT. The CLKOUT pin can be used
to synchronize the converter data to the digital system. This
is necessary when using a sinusoidal encode. In all CMOS
modes, A bus data will be updated just after CLKOUTA rises
and can be latched on the falling edge of CLKOUTA. In demux
CMOS mode with interleaved update, B bus data will be
updated just after CLKOUTB rises and can be latched on the
falling edge of CLKOUTB. In demux CMOS mode with si-
multaneous update, B bus data will be updated just after
CLKOUTB falls and can be latched on the rising edge of
CLKOUTB. In LVDS mode, data will be updated just after
CLKOUT
edge of CLKOUT
DD
DD
DD
+
/CLKOUT
2’s Complement
2’s Complement
Output Format
DD
Offset Binary
Offset Binary
+
/CLKOUT
–
selects offset binary output format.
rises and can be latched on the falling
DD
or 2/3V
DD
–
.
or V
DD
+
DD
/OF
logic values. Table 3
selects 2’s comple-
Cycle Stablizer
–
Clock Duty
pins indicates an
+
Off
Off
On
On
input available
22201fa