AD9265BCPZ-80 Analog Devices Inc, AD9265BCPZ-80 Datasheet - Page 26
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AD9265BCPZ-80
Manufacturer Part Number
AD9265BCPZ-80
Description
IC ADC 16BIT 80MSPS 48LFCSP
Manufacturer
Analog Devices Inc
Datasheet
1.AD9265BCPZ-125.pdf
(44 pages)
Specifications of AD9265BCPZ-80
Data Interface
Serial, SPI™
Number Of Bits
16
Sampling Rate (per Second)
80M
Number Of Converters
1
Power Dissipation (max)
258mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-VFQFN, CSP Exposed Pad
Resolution (bits)
16bit
Sampling Rate
80MSPS
Input Channel Type
Differential
Supply Voltage Range - Analog
1.7V To 1.9V
Supply Voltage Range - Digital
1.7V To 1.9V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9265BCPZ-80
Manufacturer:
ADI/亚德诺
Quantity:
20 000
AD9265
Dither
The AD9265 has an optional dither mode that can be selected
either through the SPI bus or by using the DITHER pin. Dithering
is the act of injecting a known but random amount of white noise,
commonly referred to as dither, into the input of the ADC.
Dithering has the effect of improving the local linearity at
various points along the ADC transfer function. Dithering
can significantly improve the SFDR when quantizing small
signal inputs, typically when the input level is below −6 dBFS.
As shown in Figure 65, the dither that is added to the input of
the ADC through the dither DAC is precisely subtracted out
digitally to minimize SNR degradation. When dithering is enabled,
the dither DAC is driven by a pseudorandom number generator
(PN gen). In the AD9265, the dither DAC is precisely calibrated
to result in only a very small degradation in SNR and SINAD.
The typical SNR and SINAD degradation values, with dithering
enabled, are only 1 dB and 0.8 dB, respectively.
Large Signal FFT
In most cases, dithering does not improve SFDR for large signal
inputs close to full scale, for example, with a −1 dBFS input. For
large signal inputs, the SFDR is typically limited by front-end
sampling distortion, which dithering cannot improve. However,
even for such large signal inputs, dithering may be useful for
certain applications because it makes the noise floor whiter.
As is common in pipeline ADCs, the AD9265 contains small
DNL errors caused by random component mismatches that
produce spurs or tones that make the noise floor somewhat
randomly colored part-to-part. Although these tones are
typically at very low levels and do not limit SFDR when the
ADC is quantizing large signal inputs, dithering converts these
tones to noise and produces a whiter noise floor.
Small Signal FFT
For small signal inputs, the front-end sampling circuit typically
contributes very little distortion, and, therefore, the SFDR is likely
to be limited by tones caused by DNL errors due to random com-
ponent mismatches. Therefore, for small signal inputs (typically,
those below −6 dBFS), dithering can significantly improve
SFDR by converting these DNL tones to white noise.
VIN
DITHER
PN GEN
DAC
Figure 65. Dither Block Diagram
DITHER ENABLE
ADC CORE
DOUT
Rev. A | Page 26 of 44
Static Linearity
Dithering also removes sharp local discontinuities in the INL
transfer function of the ADC and reduces the overall peak-to-
peak INL.
In receiver applications, utilizing dither helps to reduce DNL errors
that cause small signal gain errors. Often this issue is overcome
by setting the input noise 5 dB to 10 dB above the converter
noise. By utilizing dither within the converter to correct the
DNL errors, the input noise requirement can be reduced.
Differential Input Configurations
Optimum performance is achieved while driving the AD9265 in a
differential input configuration. For baseband applications, the
AD8138, ADA4937-2, and
excellent performance and a flexible interface to the ADC.
The output common-mode voltage of the ADA4938 is easily set
with the VCM pin of the AD9265 (see Figure 66), and the
driver can be configured in the filter topology shown to provide
band limiting of the input signal.
VIN
For baseband applications where SNR is a key parameter,
differential transformer coupling is the recommended input
configuration. An example is shown in Figure 67. To bias the
analog input, the VCM voltage can be connected to the center
tap of the secondary winding of the transformer.
The signal characteristics must be considered when selecting
a transformer. Most RF transformers saturate at frequencies
below a few megahertz (MHz). Excessive signal power can also
cause core saturation, which leads to distortion.
At input frequencies in the second Nyquist zone and above, the
noise performance of most amplifiers is not adequate to achieve
the true SNR performance of the AD9265. For applications in
2V p-p
0.1µF
Figure 66. Differential Input Configuration Using the ADA4938-2
76.8Ω
Figure 67. Differential Transformer-Coupled Configuration
49.9Ω
120Ω
90Ω
0.1µF
ADA4938-2
200Ω
200Ω
ADA4938-2
R1
R1
33Ω
33Ω
C2
C1
C2
15pF
5pF
differential drivers provide
15pF
R2
R2
15Ω
15Ω
VIN+
VIN–
VIN+
VIN–
ADC
ADC
VCM
AVDD
VCM