MX7705EWE+ Maxim Integrated Products, MX7705EWE+ Datasheet - Page 23

• Manufacturer Part Number: MX7705EWE+
• Description: IC ADC 16BIT 2CH 16-SOIC
• Manufacturer: Maxim Integrated Products

Specifications of MX7705EWE+

• Number Of Bits: 16
• Sampling Rate (per Second): 500
• Data Interface: MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 6. Communications Register
Table 7. Register Selection
* The test register is used for factory testing only.
Table 8. Channel Selection
Table 9. Setup Register
ZERO: (Default = 0) Zero Bit. This is a read-only bit.
Values written to this bit are ignored.
CLKDIS: (Default = 0) Clock-Disable Bit. Set CLKDIS =
1 to disable the clock when using a crystal or resonator
across CLKIN and CLKOUT. Set CLKDIS = 1 to disable
CLKOUT when using a CMOS clock source at CLKIN.
CLKOUT is held low during clock disable to save
power. Set CLKDIS = 0 to allow other devices to use
the output signal on CLKOUT as a clock source and/or
to enable the external oscillator.
Name
Defaults
Name
Defaults
FUNCTION
FUNCTION
RS2
0
0
0
0
1
1
1
1
CH1
0
0
1
1
RS1
START/DATA READY
FIRST BIT (MSB)
0
0
1
1
0
0
1
1
COMMUNICATION
MODE CONTROL
FIRST BIT (MSB)
MD1
______________________________________________________________________________________
0
0/DRDY
0
RS0
0
1
0
1
0
1
0
1
MD0
0
CH0
0
1
0
1
Communications Register
G2
RS2
0
REGISTER SELECT
PGA GAIN CONTROL
0
Setup Register
Offset Register
Clock Register
Test Register*
Data Register
No Operation
Gain Register
REGISTER
16-Bit, Low-Power, 2-Channel,
RS1
0
G1
0
RS0
AIN1+
AIN2+
0
AIN1-
AIN1-
AIN+
G0
0
CLKDIV: (Default = 0) Clock-Divider Control Bit. The
MX7705 has an internal clock divider. Set this bit to 1 to
divide the input clock by two. When this bit is set to 0, the
MX7705 operates at the external oscillator frequency.
CLK: (Default = 1) Clock Bit. Set CLK = 1 for f
2.4576MHz with CLKDIV = 0, or 4.9152MHz with
CLKDIV = 1.
READ/WRITE
POWER-ON RESET STATUS
BIPOLAR/UNIPOLAR
SELECT
R/W
0
0x57 61 AB
0x1F 40 00
MODE
B/U
0
0x00
0x01
0x05
N/A
N/A
—
Sigma-Delta ADC
AIN1-
AIN2-
AIN1-
AIN2-
POWER-DOWN
AIN-
MODE
PD
0
BUFFER ENABLE
REGISTER SIZE (BITS)
BUF
0
REGISTER PAIR
CHANNEL SELECT
OFFSET/GAIN
CH1
0
16
24
24
—
8
8
8
8
(LSB)
0
1
0
2
CLKIN
FSYNC
FSYNC
(LSB)
CH0
0
1
23
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