LTC1401CS8 Linear Technology, LTC1401CS8 Datasheet - Page 4

• Manufacturer Part Number: LTC1401CS8
• Description: IC A/D CONV 12BIT W/SHTDN 8-SOIC
• Manufacturer: Linear Technology

Specifications of LTC1401CS8

• Number Of Bits: 12
• Sampling Rate (per Second): 200k
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 30mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

TI I G CHARACTERISTICS
LTC1401
SYMBOL
f
t
t
f
t
t
t
t
t
t
t
t
t
t
t
t
t
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: When these pin voltages are taken below GND or above V
will be clamped by internal diodes. This product can handle input currents
greater than 40mA without latch-up if the pin is driven below GND or
above V
Note 4: When these pin voltages are taken below GND, they will be clamped
by internal diodes. This product can handle input currents greater than 40mA
without latch-up if the pin is driven below GND. These pins are not clamped
to V
unless otherwise noted specifications are at T
4
SAMPLE(MAX)
CONV
ACQ
CLK
CLK
WK(NAP)
1
2
3
4
5
6
7
8
9
10
11
W U
CC
.
CC
.
PARAMETER
Maximum Sampling Frequency
Conversion Time
Acquisition Time
CLK Frequency
CLK Pulse Width
Time to Wake Up from Nap Mode
CLK Pulse Width to Return to Active Mode
CONV↑ to CLK↑ Setup Time
CONV↑ After Leading CLK↑
CONV Pulse Width
Time from CLK↑ to Sample Mode
Aperture Delay of Sample-and-Hold
Minimum Delay Between Conversion
Delay Time, CLK↑ to D
Delay Time, CLK↑ to D
Time from Previous Data Remains Valid After CLK↑
Minimum Time Between Nap/Sleep Request to Wake Up Request (Notes 5 and 8)
OUT
OUT
Hi-Z
Valid
A
= 25°C. V
The
CC
●
CC
= 3V, f
, they
denotes specifications which apply over the full operating temperature range,
SAMPLE
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: The rising edge of CONV starts a conversion. If CONV returns low
at a bit decision point during the conversion, it can create small errors. For
best performance, ensure that CONV returns low either within 120ns after
the conversion starts (i.e., before the first bit decision) or after the 14
clock cycles. (Figure 13 Timing Diagram).
Note 8: If this timing specification is not met, the device may not respond
to a request for a conversion. To recover from this condition a NAP
request is required.
= 200kHz, t
CONDITIONS
f
(Notes 5 and 8)
(Note 7)
Jitter < 50ps
(Note 5)
C
C
C
CLK
LOAD
LOAD
LOAD
= 3.2MHz
= 20pF
= 20pF
= 20pF
r
= t
f
= 5ns, unless otherwise specified.
●
●
●
●
●
●
●
●
●
●
●
●
●
MIN
200
100
0.1
60
60
50
15
50
0
TYP
315
350
350
80
45
60
60
50
MAX
550
120
120
4.1
3.2
UNITS
1401fa
MHz
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns