LTC1401 Linear Technology, LTC1401 Datasheet
LTC1401
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LTC1401 Summary of contents
Page 1
... Maximum DC specifications include 1LSB INL, 1LSB DNL and 45ppm/ C full-scale drift over temperature. The LTC1401 has three power saving modes: Nap and Sleep, through the serial interface and Shutdown by setting the SHDN pin to zero. In Nap mode, it consumes only 1.5mW of power and can wake up and convert immediately ...
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... Digital Input Voltage (Note 4) ....................– 0.3V to 12V Digital Output Voltage .................. – 0. Power Dissipation .............................................. 300mW Operating Ambient Temperature Range LTC1401C................................................ LTC1401I ............................................ – Operating Junction Temperature ......................... 125 C Storage Temperature Range ................. – 150 C Lead Temperature (Soldering, 10 sec).................. 300 ...
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... 2.7V – 2.7V – 200 2.7V 400 OUT OUT OUT CC LTC1401 MIN TYP MAX UNITS 12 Bits 1 LSB 1 LSB 6 LSB 8 LSB 15 LSB 10 45 ppm/ C MIN TYP MAX UNITS – 72 – ...
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... LTC1401 CHARACTERISTICS SYMBOL PARAMETER f Maximum Sampling Frequency SAMPLE(MAX) t Conversion Time CONV t Acquisition Time ACQ f CLK Frequency CLK t CLK Pulse Width CLK t Time to Wake Up from Nap Mode WK(NAP) t CLK Pulse Width to Return to Active Mode 1 t CONV to CLK Setup Time 2 t CONV After Leading CLK ...
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... SOURCE RESISTANCE ( ) LTC1401 • TPC05 Supply Current vs Temperature 12 f SAMPLE 3. 2. 1000 50 –50 – TEMPERATURE (˚C) LTC1401 • TPC08 = 200kHz 1000 LTC1401 • TPC03 1k 10k LTC1401 • TPC06 = 200kHz 100 125 75 LTC1401 • TPC09 5 ...
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... Low). The device will draw 4 this mode ZEROING SWITCH SAMPLE 12-BIT CAPACITIVE DAC 12 SUCCESSIVE APPROXIMATION REGISTER/PARALLEL TO SERIAL CONVERTER D OUT C LOAD GND SHDN COMP D OUT LTC1401 • BD01 LOAD Hi Hi-Z OL LTC1401 • TC01 ...
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... D Dynamic Performance The LTC1401 has excellent high speed sampling capabil- ity. FFT (Fast Fourier Transform) test techniques are used to test the ADC’s frequency response, distortion and noise at the rated throughput ...
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... Where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the LTC1400 • F02b second through nth harmonics. THD vs input frequency is shown in Figure 4. The LTC1401 has good distortion performance up to the Nyquist frequency and beyond. –10 –20 –30 – ...
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... S/(N+D) has dropped to 68dB (11 effective bits Driving the Analog Input The analog input of the LTC1401 is easy to drive. It draws only one small current spike while charging the sample- and-hold capacitor at the end of a conversion. During conversion, the analog input draws only a small leakage current ...
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... For zero 3 full-scale error, apply an analog input of 2.04725V ( FS – 1.5LSB or last code transition ) at the input and adjust GND until the LTC1401 output code flickers between 1111 1111 LTC1401 • F07 1110 and 1111 1111 1111. 1LSB = FS 2.048 = ...
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... Figure 10 shows the recommended system ground con- 100k LTC1401 nections. All analog circuitry grounds should be termi- R5 nated at the LTC1401 GND pin. The ground return to the 4.3k FULL-SCALE power supply from Pin 4 should be low impedance for ADJUST noise free operation. Digital circuitry grounds must be ...
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... LTC1401 enters Shutdown mode and power con- sumption drops to 13.5 W. Once SHDN goes high, the LTC1401 returns to active mode or the LTC1401 returns to active mode by pulsing the CLK signal if the device has entered Nap/Sleep mode. During the transistion from Sleep mode to active mode, ...
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... REFRDY BIT + 12-BIT DATA WORD t CONV t SAMPLE Figure 12. ADC Digital Timing Waveform CLK OUT V OL Figure 13. CLK to D Delay OUT LTC1401 ACQ SAMPLE 90% 10% LTC1401 • F13 2 HOLD REFRDY LT1401 • F12 13 ...
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... F 0 Logic Analyzer Waveforms Show 6.4 s Throughput Rate (Input Voltage = 0.765V, Output Code = 0101 1111 1010 = 1530 Data from the LTC1401 Loaded into the TMS320C50’s TRCV Register X RDY Data Stored in the TMS320C50’s Memory (in Right Justified Format 2.5MHz EXTERNAL CLOCK ...
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... AND #1FFFh, 0 SACL *+, 0 LACC AR7 SUB #0F05h,0 BCND END_TRCV, GEQ ; If the end sample address has exceeded jump SPLK #040h, IMR RETE *After Obtained the Data from LTC1401, Program Jump to END_TRCV* END_TRCV: SPLK #002h, IMR CLRC INTM SUCCESS: B SUCCESS *Fill the unused interrupt with RETE, to avoid program get “lost”* ...
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... LTC1401 U TYPICAL APPLICATIONS LTC1401 Interface to the ADSP2181’s SPORT0 (Frame Sync is Generated from RFS Logic Analyzer Waveforms Show 4.8 s Throughput Rate (Input Voltage = 1.604V, Output Code = 1100 1000 1000 = 3208 X RDY Data Stored in the ADSP2181’s Memory (Normal Mode, SLEN = ...
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... U TYPICAL APPLICATIONS THIS PROGRAM DEMONSTRATES THE LTC1401 INTERFACE TO THE ADSP-2181. FRAME SYNC PULSE IS GENERATED FROM RFS. DATA SHIFT CLOCK IS INTERNALLY GENERATED. /*Section 1: Initialization*/ .module/ram/abs = 0 adspltc; /*define the program module*/ jump start; /*jump over interrupt vectors*/ nop; nop; nop; rti; rti; rti; rti; ...
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... SRCLR 12 15 RCK SRCK 74HC595 14 4 SER QH' SRCLR 12 15 RCK SRCK QC D10 3 QD D11 74HC595 14 4 SER QE REFRDY QH' LTC1401 • TA03 ...
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... TYP 0.014 – 0.019 (0.355 – 0.483) LTC1401 0.150 – 0.157** (3.810 – 3.988 0.004 – 0.010 (0.101 – 0.254) 0.050 (1 ...
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... LTC1401 U TYPICAL APPLICATIONS Interface to the TMS320C50’s TDM Serial Port (Frame Sync is Generated from TFSX LTC1401 Interface to the ADSP2181’s SPORT0 (Frame Sync is Generated from RFS) + RELATED PARTS 12-Bit Parallel Output ADCs PART NUMBER DESCRIPTION LTC1273/LTC1275/LTC1276 Complete 5V Sampling 12-Bit ADCs with 70dB SINAD at Niquist ...