LTC2435-1CGN Linear Technology, LTC2435-1CGN Datasheet - Page 23

• Manufacturer Part Number: LTC2435-1CGN
• Description: IC ADC DIFF I/REF 20BIT 16-SSOP
• Manufacturer: Linear Technology

Specifications of LTC2435-1CGN

• Number Of Bits: 20
• Sampling Rate (per Second): 13.75
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.150", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the conver-
sion status. If the device is in the sleep state (EOC = 0), SCK
will go LOW. Once CS goes HIGH (within the time period
defined above as t
For a heavy capacitive load on the SCK pin, the internal
pull-up may not be adequate to return SCK to a HIGH level
before CS goes low again. This is not a concern under
normal conditions where CS remains LOW after detecting
EOC = 0. This situation is easily overcome by adding an
external 10k pull-up resistor to the SCK pin.
Internal Serial Clock, 2-Wire I/O,
Continuous Conversion
This timing mode uses a 2-wire, all output (SCK and SDO)
interface. The conversion result is shifted out of the device
by an internally generated serial clock (SCK) signal, see
Figure 13. CS may be permanently tied to ground, simpli-
fying the user interface or isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
(INTERNAL)
SDO
SCK
CS
CONVERSION
EOCtest
U
), the internal pull-up is activated.
BIT 23
U
EOC
BIT 22
Figure 13. Internal Serial Clock, Continuous Operation
W
ANALOG INPUT RANGE
–0.5V
BIT 21
SIG
REF
1, 7, 8, 9, 10, 15, 16
0.1V TO V
REFERENCE
U
TO 0.5V
VOLTAGE
BIT 20
MSB
1μF
2.7V TO 5.5V
REF
CC
2
3
4
5
6
BIT 19
V
REF
REF
IN
IN
GND
CC
LTC2435-1
+
–
LTC2435/
approximately 1ms after V
weak pull-up is active during the POR cycle; therefore, the
internal serial clock timing mode is automatically selected
if SCK is not externally driven LOW (if SCK is loaded such
that the internal pull-up cannot pull the pin HIGH, the
external SCK mode will be selected).
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating the
conversion has finished. The data output cycle begins on
the first rising edge of SCK and ends after the 24th rising
edge. Data is shifted out the SDO pin on each falling edge
of SCK. The internally generated serial clock is output to
the SCK pin. This signal may be used to shift the conver-
sion result into external circuitry. EOC can be latched on
the first rising edge of SCK and the last bit of the
conversion result can be latched on the 24th rising edge
of SCK. After the 24th rising edge, SDO goes HIGH (EOC
= 1) indicating a new conversion is in progress. SCK
remains HIGH during the conversion.
+
–
DATA OUTPUT
BIT 18
SDO
SCK
CS
F
O
14
13
12
11
2-WIRE
INTERFACE
V
LTC2435/LTC2435-1
CC
= 50Hz REJECTION (LTC2435)
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2435)
= 50Hz/60Hz REJECTION (LTC2435-1)
BIT 5
CC
exceeds 2.2V. An internal
BIT 0
LSB
CONVERSION
23
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