LTC1407CMSE#TR Linear Technology, LTC1407CMSE#TR Datasheet - Page 5

• Manufacturer Part Number: LTC1407CMSE#TR
• Description: IC ADC 12BIT 3MSPS SAMPLE 10MSOP
• Manufacturer: Linear Technology

Specifications of LTC1407CMSE#TR

• Number Of Bits: 12
• Sampling Rate (per Second): 3M
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 14mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width) Exposed Pad
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SYMBOL
t
t
t
t
t
TIMING CHARACTERISTICS
range, otherwise specifi cations are at T
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground GND.
Note 3: When these pins are taken below GND or above V
clamped by internal diodes. This product can handle input currents greater
than 100mA below GND or greater than V
Note 4: Offset and range specifi cations apply for a single-ended CH0
input with CH0
Note 5: Integral linearity is tested with an external 2.55V reference and is
defi ned as the deviation of a code from the straight line passing through
the actual endpoints of a transfer curve. The deviation is measured from
the center of quantization band.
Note 6: Guaranteed by design, not subject to test.
Note 7: Recommended operating conditions.
Note 8: The analog input range is defi ned for the voltage difference
between CH0
Note 9: The absolute voltage at CH0
within this range.
TYPICAL PERFORMANCE CHARACTERISTICS
7
8
9
10
12
12.0
11.5
11.0
10.5
10.0
9.5
9.0
8.5
8.0
0.1
ENOBs and SINAD
vs Input Sinewave Frequency
+
–
and CH0
or CH1
PARAMETER
32nd SCK↑ to CONV↑ Interval (Affects Acquisition Period)
Minimum Delay from SCK to Valid Bits 0 Through 11
SCK to Hi-Z at SDO
Previous SDO Bit Remains Valid After SCK
V
REF
FREQUENCY (MHz)
1
Settling Time After Sleep-to-Wake Transition
–
–
grounded and using the internal 2.5V reference.
or CH1
+
10
and CH1
+
, CH0
DD
–
1407 G01
–
.
, CH1
without latchup.
100
A
= 25°C. V
74
71
68
65
62
59
56
53
50
+
and CH1
DD
DD
–
The
–104
, they will be
–44
–50
–56
–62
–68
–74
–80
–86
–92
–98
must be
= 3V.
0.1
l
THD, 2nd and 3rd
vs Input Frequency
+
denotes the specifi cations which apply over the full operating temperature
or CH1
+
FREQUENCY (MHz)
1
Note 10: If less than 3ns is allowed, the output data will appear one
clock cycle later. It is best for CONV to rise half a clock before SCK, when
running the clock at rated speed.
Note 11: Not the same as aperture delay. Aperture delay (1ns) is the
difference between the 2.2ns delay through the sample-and-hold and the
1.2ns CONV to Hold mode delay.
Note 12: The rising edge of SCK is guaranteed to catch the data coming
out into a storage latch.
Note 13: The time period for acquiring the input signal is started by the
32nd rising clock and it is ended by the rising edge of CONV.
Note 14: The internal reference settles in 2ms after it wakes up from Sleep
mode with one or more cycles at SCK and a 10μF capacitive load.
Note 15: The full power bandwidth is the frequency where the output code
swing drops by 3dB with a 2.5V
Note 16: Maximum clock period guarantees analog performance during
conversion. Output data can be read with an arbitrarily long clock period.
Note 17: The LTC1407A is measured and specifi ed with 14-bit resolution
(1LSB = 152μV) and the LTC1407 is measured and specifi ed with 12-bit
resolution (1LSB = 610μV).
CONDITIONS
(Notes 6, 7, 13)
(Notes 6, 12)
(Notes 6, 12)
(Notes 6, 12)
(Notes 6, 14)
THD
10
3rd
2nd
V
DD
1407 G02
= 3V, T
100
LTC1407/LTC1407A
A
104
98
92
86
80
74
68
62
56
50
44
= 25°C (LTC1407A)
MIN
P-P
45
0.1
8
6
2
SFDR vs Input Frequency
input sine wave.
TYP
2
FREQUENCY (MHz)
1
MAX
10
UNITS
1407 G19
1407fb
5
100
ms
ns
ns
ns
ns