LTC1407CMSE#TR Linear Technology, LTC1407CMSE#TR Datasheet - Page 8

• Manufacturer Part Number: LTC1407CMSE#TR
• Description: IC ADC 12BIT 3MSPS SAMPLE 10MSOP
• Manufacturer: Linear Technology

Specifications of LTC1407CMSE#TR

• Number Of Bits: 12
• Sampling Rate (per Second): 3M
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 14mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width) Exposed Pad
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

BLOCK DIAGRAM
LTC1407/LTC1407A
PIN FUNCTIONS
CH0
fully differentially with respect to CH0
differential swing and a 0 to V
CH0
differentially with respect to CH0
ferential swing and a 0 to V
V
a solid analog ground plane with a 10μF ceramic capacitor
(or 10μF tantalum in parallel with 0.1μF ceramic). Can be
overdriven by an external reference voltage ≥ 2.55V and
≤V
CH1
fully differentially with respect to CH1
differential swing and a 0 to V
CH1
differentially with respect to CH1
ferential swing and a 0 to V
GND (Pins 6, 11): Ground and Exposed Pad. This single
ground pin and the Exposed Pad must be tied directly to
the solid ground plane under the part. Keep in mind that
analog signal currents and digital output signal currents
fl ow through these connections.
8
REF
DD
+
–
+
–
(Pin 3): 2.5V Internal Reference. Bypass to GND and
.
(Pin 2): Inverting Channel 0. CH0
(Pin 5): Inverting Channel 1. CH1
(Pin 1): Noninverting Channel 0. CH0
(Pin 4): Noninverting Channel 1. CH1
10μF
CH0
CH0
CH1
CH1
+
–
+
–
DD
DD
11
1
2
4
5
3
6
DD
DD
V
GND
absolute input range.
absolute input range.
REF
EXPOSED PAD
+
–
+
–
+
+
absolute input range.
absolute input range.
S AND H
S AND H
with a –2.5V to 0V dif-
with a –2.5V to 0V dif-
–
–
with a 0V to 2.5V
with a 0V to 2.5V
–
–
operates fully
operates fully
MUX
REFERENCE
+
+
2.5V
operates
operates
14-BIT ADC
3Msps
10μF
V
supplies 3V to the entire chip. Bypass to GND pin and
solid analog ground plane with a 10μF ceramic capacitor
(or 10μF tantalum) in parallel with 0.1μF ceramic. Keep in
mind that internal analog currents and digital output signal
currents fl ow through this pin. Care should be taken to
place the 0.1μF bypass capacitor as close to Pins 6 and 7
as possible.
SDO (Pin 8): Three-State Serial Data Output. Each pair of
output data words represent the two analog input channels
at the start of the previous conversion.
SCK (Pin 9): External Clock Input. Advances the conver-
sion process and sequences the output data on the rising
edge. One or more pulses wake from sleep.
CONV (Pin 10): Convert Start. Holds the two analog input
signals and starts the conversion on the rising edge. Two
pulses with SCK in fi xed high or fi xed low state starts Nap
mode. Four or more pulses with SCK in fi xed high or fi xed
low state starts Sleep mode.
3V
7
DD
V
DD
(Pin 7): 3V Positive Supply. This single power pin
OUTPUT
THREE-
TIMING
SERIAL
LOGIC
STATE
PORT
LTC1407A
10
8
9
1407A BD
SDO
CONV
SCK
1407fb