LTC1407CMSE-1#TR Linear Technology, LTC1407CMSE-1#TR Datasheet - Page 16

• Manufacturer Part Number: LTC1407CMSE-1#TR
• Description: IC ADC 12BIT 3MSPS SAMPLE 10MSOP
• Manufacturer: Linear Technology

Specifications of LTC1407CMSE-1#TR

• Number Of Bits: 12
• Sampling Rate (per Second): 3M
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 14mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width) Exposed Pad
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIONS INFORMATION
LTC1407-1/LTC1407A-1
1.25V
Board Layout and Bypassing
Wire wrap boards are not recommended for high resolu-
tion and/or high speed A/D converters. To obtain the best
performance from the LTC1407-1/LTC1407A-1, a printed
circuit board with ground plane is required. Layout for
the printed circuit board should ensure that digital and
analog signal lines are separated as much as possible. In
particular, care should be taken not to run any digital track
alongside an analog signal track. If optimum phase match
between the inputs is desired, the length of the four input
wires of the two input channels should be kept matched.
But each pair of input wires to the two input channels
should be kept separated by a ground trace to avoid high
frequency crosstalk between channels.
High quality tantalum and ceramic bypass capacitors
should be used at the V
Block Diagram on the fi rst page of this data sheet. For
optimum performance, a 10μF surface mount tantalum
capacitor with a 0.1μF ceramic is recommended for the V
and V
such as X5R or X7R may be used. The capacitors must be
located as close to the pins as possible. The traces con-
necting the pins and the bypass capacitors must be kept
short and should be made as wide as possible. The V
bypass capacitor returns to GND (Pin 6) and the V
pass capacitor returns to the Exposed Pad ground (Pin 11).
16
Figure 6a. The LT1819 Driving the LTC1407A-1 Differentially
MAX
V
P-P
IN
REF
pins. Alternatively, 10μF ceramic chip capacitors
499Ω
R4
499Ω
–
1/2 LT1819
+
R3
–
1/2 LT1819
+
U1
U2
–5V
5V
0.1μF
0.1μF
DD
C5
C6
and V
1μF
1μF
C3
C4
REF
R5
1k
R6
1k
51Ω
51Ω
R1
R2
pins as shown in the
1.5V
CM
C1
47pF
C2
47pF
+CH0 OR
+CH1
–CH0 OR
–CH1
LTC1407A-1
REF
1407A F06a
by-
DD
DD
Care should be taken to place the 0.1μF V
pacitor as close to Pins 6 and 7 as possible.
Figure 7 shows the recommended system ground connec-
tions. All analog circuitry grounds should be terminated
Figure 6b. LTC1407-1 6MHz Sine Wave 4096 Point FFT Plot
with the LT1819 Driving the Inputs Differentially
–100
–110
–120
–20
–30
–40
–50
–70
–10
–60
–80
–90
0
0
Figure 7. Recommended Layout
185k
FREQUENCY (Hz)
371k
556k
14031 F06b
741k
DD
bypass ca-
1407-1 F07
14071fb