LTC1400CS8 Linear Technology, LTC1400CS8 Datasheet - Page 11

IC A/D CONV 12BIT W/SHTDN 8-SOIC

LTC1400CS8

Manufacturer Part Number
LTC1400CS8
Description
IC A/D CONV 12BIT W/SHTDN 8-SOIC
Manufacturer
Linear Technology
Datasheet

Specifications of LTC1400CS8

Number Of Bits
12
Sampling Rate (per Second)
400k
Data Interface
MICROWIRE™, Serial, SPI™
Number Of Converters
1
Power Dissipation (max)
160mW
Voltage Supply Source
Dual ±
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (0.154", 3.90mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LTC1400CS8
Manufacturer:
LT
Quantity:
10 000
Part Number:
LTC1400CS8
Manufacturer:
LINEAR/凌特
Quantity:
20 000
APPLICATIO S I FOR ATIO
0V TO 4.096V
Figure 10c. LTC1400 Bipolar Offset and Full-Scale Adjust Circuit
ANALOG
±2.048V
INPUT
ANALOG
Figure 10b. LTC1400 Offset and Full-Scale Adjust Circuit
V
IN
ADDITIONAL PINS OMITTED FOR CLARITY
±20LSB TRIM RANGE
INPUT
5V
Figure 10a. LTC1400 Full-Scale Adjust Circuit
50Ω
R1
10k
R1
10k
10k
R1
R2
10k
R2
10k
R2
10k
R9
20Ω
U
+
R3
10k
A1
+
U
+
A1
A1
100Ω
FULL-SCALE
R4
ADJUST
W
R4
100k
R5
4.3k
FULL-SCALE
ADJUST
R3
100k
R6
200Ω
R4
100k
R5
4.3k
FULL-SCALE
ADJUST
R3
100k
R6
400Ω
100k
R7
A
GND
100k
LTC1400
R7
IN
A
LTC1400
–5V
IN
5V
U
A
LTC1400
R8
20k
OFFSET
ADJUST
IN
1400 F10a
5V
R8
10k
OFFSET
ADJUST
1400 F10c
1400 F10b
error adjustment. Figure 10b shows offset and full-scale
adjustment. Offset error must be adjusted before full-
scale error. Zero offset is achieved by applying 0.5mV
(i.e., 0.5LSB) at the input and adjusting the offset trim
until the LTC1400 output code flickers between 0000
0000 0000 and 0000 0000 0001. For zero full-scale er-
ror, apply an analog input of 4.0945V (FS – 1.5LSB or
last code transition) at the input and adjust R5 until the
LTC1400 output code flickers between 1111 1111 1110
and 1111 1111 1111.
Bipolar Offset and Full-Scale Error Adjustments
Bipolar offset and full-scale errors are adjusted in a similar
fashion to the unipolar case. Bipolar offset error adjust-
ment is achieved by applying an input voltage of –0.5mV
(–0.5LSB) to the input in Figure 10c and adjusting the
op amp until the ADC output code flickers between 0000
0000 0000 and 1111 1111 1111. For full-scale adjustment,
an input voltage of 2.0465V (FS – 1.5LSBs) is applied to
the input and R5 is adjusted until the output code flickers
between 0111 1111 1110 and 0111 1111 1111.
Board Layout and Bypassing
To obtain the best performance from the LTC1400, a
printed circuit board is required. Layout for the printed
circuit board should ensure that digital and analog signal
lines are separated as much as possible. In particular, care
should be taken not to run any digital track alongside an
analog signal track or underneath the ADC. The analog
input should be screened by GND.
High quality tantalum and ceramic bypass capacitors
should be used at the V
Typical Application on the first page of this data sheet.
For the bipolar mode, a 0.1μF ceramic provides adequate
bypassing for the V
10μF surface mount AVX capacitor with a 0.1μF ceramic
is recommended for the V
must be located as close to the pins as possible. The traces
connecting the pins and the bypass capacitors must be
kept short and should be made as wide as possible. In
unipolar mode operation, V
any noise source before shorting to the GND pin.
SS
pin. For optimum performance, a
CC
CC
and V
and V
SS
should be isolated from
REF
REF
pins as shown in the
pins. The capacitors
LTC1400
11
1400fa

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