LTC2402IMS Linear Technology, LTC2402IMS Datasheet - Page 12

• Manufacturer Part Number: LTC2402IMS
• Description: IC ADC 24BIT 2CH MICROPWR 10MSOP
• Manufacturer: Linear Technology

Specifications of LTC2402IMS

• Number Of Bits: 24
• Sampling Rate (per Second): 7.5
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
LTC2401/LTC2402
Bit 29 (third output bit) is the conversion result sign indi-
cator (SIG). If V
bit is LOW. The sign bit changes state during the zero code.
Bit 28 (forth output bit) is the extended input range (EXR)
indicator. If the input is within the normal input range
0 V
normal input range, V
The function of these bits is summarized in Table 1.
Table 1. LTC2401/LTC2402 Status Bits
Input Range
V
0 < V
V
V
Bit 27 (fifth output bit) is the most significant bit (MSB).
Bits 27-4 are the 24-bit conversion result MSB first.
Bit 4 is the least significant bit (LSB).
Bits 3-0 are sub LSBs below the 24-bit level. Bits 3-0 may
be included in averaging or discarded without loss of
resolution.
Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 3. Whenever CS is HIGH, SDO
remains high impedance and any SCK clock pulses are
ignored by the internal data out shift register.
In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes real time from
12
IN
IN
IN
> V
= 0
< 0
IN
IN
REF
+
/0
V
–
REF
V
REF
SDO
SCK
, this bit is LOW. If the input is outside the
CS
IN
Bit 31
is >0, this bit is HIGH. If V
EOC
U
Hi-Z
0
0
0
0
SLEEP
IN
> V
U
BIT 31
REF
EOC
CH0/CH1
Bit 30
0/1
0/1
0/1
0/1
1
or V
CH0/CH1
BIT 30
IN
W
< 0, this bit is HIGH.
2
Bit 29
SIG
1/0
1
1
0
BIT 29
IN
SIG
Figure 3. Output Data Timing
U
is <0, this
3
Bit 28
EXR
1
0
0
1
BIT 28
EXT
4
DATA OUTPUT
BIT 27
MSB
HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external micro-
controller. Bit 31 (EOC) can be captured on the first rising
edge of SCK. Bit 30 is shifted out of the device on the first
falling edge of SCK. The final data bit (Bit 0) is shifted out
on the falling edge of the 31st SCK and may be latched on
the rising edge of the 32nd SCK pulse. On the falling edge
of the 32nd SCK pulse, SDO goes HIGH indicating a new
conversion cycle has been initiated. This bit serves as EOC
(Bit 31) for the next conversion cycle. Table 2 summarizes
the output data format.
As long as the voltage on the V
the – 0.3V to (V
range, a conversion result is generated for any input value
from – 0.125 • V
greater than 1.125 • V
to the value corresponding to 1.125 • V
voltages below – 0.125 • V
clamped to the value corresponding to – 0.125 • V
Frequency Rejection Selection (F
The LTC2401/LTC2402 internal oscillator provides better
than 110dB normal mode rejection at the line frequency
and all its harmonics for 50Hz 2% or 60Hz 2%. For
60Hz rejection, F
(Pin 6) while for 50Hz rejection the F
connected to V
The selection of 50Hz or 60Hz rejection can also be made
by driving F
change during the sleep or data output states will not
5
27
O
to an appropriate logic level. A selection
CC
CC
LSB
BIT 4
REF
O
(Pin 1).
+ 0.3V) absolute maximum operating
(Pin 10) should be connected to GND
24
28
REF
to 1.125 • V
, the conversion result is clamped
BIT 0
REF
32
IN
, the conversion result is
pin is maintained within
REF
CONVERSION
O
Pin Connection)
. For input voltages
24012 F03
O
pin should be
REF
. For input
REF
.