LTC1609CSW#TRPBF Linear Technology, LTC1609CSW#TRPBF Datasheet - Page 15

• Manufacturer Part Number: LTC1609CSW#TRPBF
• Description: IC ADC SRL 16BIT 200KSPS 20-SOIC
• Manufacturer: Linear Technology

Specifications of LTC1609CSW#TRPBF

• Number Of Bits: 16
• Sampling Rate (per Second): 200k
• Data Interface: Serial
• Number Of Converters: 1
• Power Dissipation (max): 100mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIO S I FOR ATIO
External Clock Mode
With the EXT/INT pin tied high, the DATACLK pin becomes
a digital input and the LTC1609 can accept an externally
supplied data clock. There are several ways in which the
conversion results can be clocked out. The data can be
clocked out during or after a conversion with a continuous
or discontinuous data clock. Figures 9 to 12 show the
timing diagram for each of these methods.
External Discontinuous Data Clock Data Read
After the Conversion
Figure 9 shows how the result from the current conver-
sion can be read out after the conversion has been
completed. The externally supplied data clock is running
discontinuously. R/C is used to initiate a conversion with
CS tied low. The conversion starts on the falling edge of
R/C. R/C should be returned high within 1.2 s to prevent
the transition from disturbing the conversion. After the
conversion has been completed (BUSY returning high), a
EXTERNAL
DATACLK
BUSY
SYNC
DATA
TAG
R/C
U
Figure 9. Conversion and Read Timing Using an External Discontinuous Data Clock
(EXT/INT Tied High, CS Tied Low). Read Conversion Result After the Conversion
t
2
t
1
U
t
3
W
t
t
13
17
t
21
0
U
t
TAG0
12
t
t
23
12
1
(MSB)
TAG1
t
B15
14
t
t
18
24
2
pulse on the SYNC pin will be generated on the rising edge
of DATACLK #0. The SYNC output can be captured on the
falling edge of DATACLK #0 or on the rising edge of
DATACLK #1. After the rising edge of DATACLK #1, the
SYNC output will go low and the MSB will be clocked out
on the DATA pin. This bit can be latched on the falling edge
of DATACLK #1 or on the rising edge of DATACLK #2. The
LSB will be valid on the falling edge of DATACLK #16 or the
rising edge of DATACLK #17. After the rising edge of
DATACLK #17 the DATA pin will take on the value of the
TAG pin that occurred at the rising edge of DATACLK #1.
A minimum of 17 clock pulses are required if the data is
captured on falling clock edges.
Using the highest frequency permitted for DATACLK
(20MHz), shifting the data out after the conversion will
not degrade the 200kHz throughput. This method mini-
mizes the possible external disturbances that can occur
while a conversion is in progress and will yield the best
performance.
TAG2
B14
3
TAG3
B13
15
TAG15
B1
16
TAG16
B0
17
TAG17
TAG0
LTC1609
TAG18
TAG1
15
TAG19
TAG2
1606 F09
1609fa