LTC2240IUP-10#PBF Linear Technology, LTC2240IUP-10#PBF Datasheet - Page 21
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LTC2240IUP-10#PBF
Manufacturer Part Number
LTC2240IUP-10#PBF
Description
IC ADC 10BIT 170MSPS 64-QFN
Manufacturer
Linear Technology
Datasheet
1.LTC2240CUP-10TRPBF.pdf
(28 pages)
Specifications of LTC2240IUP-10#PBF
Number Of Bits
10
Sampling Rate (per Second)
170M
Data Interface
Parallel
Number Of Converters
1
Power Dissipation (max)
638mW
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-WFQFN, Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
APPLICATIONS INFORMATION
Data Format
The LTC2240-10 parallel digital output can be selected
for offset binary or 2’s complement format. The format
is selected with the MODE pin. Connecting MODE to GND
or 1/3V
MODE to 2/3V
format. An external resistor divider can be used to set the
1/3V
states for the MODE pin.
Table 3. MODE Pin Function
MODE PIN
GND
1/3V
2/3V
V
Overfl ow Bit
An overfl ow output bit indicates when the converter is
overranged or underranged. In CMOS mode, a logic high
on the OFA pin indicates an overfl ow or underfl ow on the
A data bus, while a logic high on the OFB pin indicates an
overfl ow or underfl ow on the B data bus. In LVDS mode,
a differential logic high on the OF
overfl ow or underfl ow.
DD
LTC2240-10
LATCH
FROM
DATA
DD
DD
OE
DD
DD
Figure 13a. Digital Output Buffer in CMOS Mode
or 2/3V
PREDRIVER
LOGIC
selects offset binary output format. Connecting
V
DD
DD
DD
OUTPUT FORMAT
2’s Complement
2’s Complement
Offset Binary
Offset Binary
or V
logic values. Table 3 shows the logic
DD
selects 2’s complement output
V
DD
+
/OF
OV
–
CYCLE STABILIZER
DD
pins indicates an
CLOCK DUTY
43Ω
224010 F13a
Off
On
On
Off
OV
OGND
DD
TYPICAL
DATA
OUTPUT
0.1μF
0.5V
TO 2.625V
Output Clock
The ADC has a delayed version of the ENC
as a digital output, CLKOUT. The CLKOUT pin can be used
to synchronize the converter data to the digital system.
This is necessary when using a sinusoidal encode. In
all CMOS modes, A bus data will be updated just after
CLKOUTA rises and can be latched on the falling edge of
CLKOUTA. In demux CMOS mode with interleaved update,
B bus data will be updated just after CLKOUTB rises and
can be latched on the falling edge of CLKOUTB. In demux
CMOS mode with simultaneous update, B bus data will be
updated just after CLKOUTB falls and can be latched on
the rising edge of CLKOUTB. In LVDS mode, data will be
updated just after CLKOUT
latched on the falling edge of CLKOUT
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OV
to the same power supply as for the logic being driven.
For example if the converter is driving a DSP powered
by a 1.8V supply then OV
1.8V supply.
LTC2240-10
–
+
Figure 13b. Digital Output in LVDS Mode
D
D
1.25V
10k
DD
10k
3.5mA
+
/CLKOUT
should be tied to that same
LTC2240-10
224010 F13b
D
D
–
+
OUT
OUT
DD
100Ω
/CLKOUT
rises and can be
+
+
–
, should be tied
OGND
input available
OV
DD
0.1μF
RECEIVER
–
21
.
LVDS
224010fb
2.5V