LTC1750IFW Linear Technology, LTC1750IFW Datasheet - Page 18

• Manufacturer Part Number: LTC1750IFW
• Description: IC ADC 14BIT 80MSPS SMPL 48TSSOP
• Manufacturer: Linear Technology

Specifications of LTC1750IFW

• Number Of Bits: 14
• Sampling Rate (per Second): 80M
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 1.69W
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TFSOP (0.240", 6.10mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
LTC1750
REFLA. These capacitors should be as close to the device
as possible (1.5mm or less). Size 0402 ceramic capacitors
are recomended. The large 4.7 F capacitor between REFHA
and REFLA can be somewhat further away. The traces
connecting the pins and bypass capacitors must be kept
short and should be made as wide as possible.
The LTC1750 differential inputs should run parallel and
close to each other. The input traces should be as short as
possible to minimize capacitance and to minimize noise
pickup.
An analog ground plane separate from the digital process-
ing system ground should be used. All ADC ground pins
labeled GND should connect to this plane. All ADC V
bypass capacitors, reference bypass capacitors and input
filter capacitors should connect to this analog plane. The
LTC1750 has three output driver ground pins, labeled
OGND (Pins 27, 38 and 47). These grounds should con-
nect to the digital processing system ground. The output
driver supply, OV
18
DD
U
should be connected to the digital
U
W
U
DD
processing system supply. OV
bypass to the digital system ground. The digital process-
ing system ground should be connected to the analog
plane at ADC OGND (Pin 38).
HEAT TRANSFER
Most of the heat generated by the LTC1750 is transferred
from the die through the package leads onto the printed
circuit board. In particular, ground pins 12, 13, 36 and 37
are fused to the die attach pad. These pins have the lowest
thermal resistance between the die and the outside envi-
ronment. It is critical that all ground pins are connected to
a ground plane of sufficient area. The layout of the evalu-
ation circuit shown on the following pages has a low ther-
mal resistance path to the internal ground plane by using
multiple vias near the ground pins. A ground plane of this
size results in a thermal resistance from the die to ambient
of 35 C/W. Smaller area ground planes or poorly connected
ground pins will result in higher thermal resistance.
DD
bypass capacitors should
1750f