LTC2259CUJ-16#PBF Linear Technology, LTC2259CUJ-16#PBF Datasheet - Page 18

• Manufacturer Part Number: LTC2259CUJ-16#PBF
• Description: IC ADC 16BIT 80MSPS 40QFN
• Manufacturer: Linear Technology

Specifications of LTC2259CUJ-16#PBF

• Number Of Bits: 16
• Sampling Rate (per Second): 80M
• Data Interface: Serial, Parallel
• Number Of Converters: 1
• Power Dissipation (max): 201mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LTC2259-16
APPLICATIONS INFORMATION
Phase-Shifting the Output Clock
In full-rate CMOS mode the data output bits normally
change at the same time as the falling edge of CLKOUT
so the rising edge of CLKOUT
output data. In double-data rate CMOS and LVDS modes
the data output bits normally change at the same time as
the falling and rising edges of CLKOUT
setup-and-hold time when latching the data, the CLKOUT
signal may need to be phase shifted relative to the data
output bits. Most FPGAs have this feature; this is generally
the best place to adjust the timing.
The LTC2259-16 can also phase shift the CLKOUT
OUT
register A2. The output clock can be shifted by 0°, 45°,
90° or 135°. To use the phase shifting feature the clock
duty cycle stabilizer must be turned on. Another con-
trol register bit can invert the polarity of CLKOUT
CLKOUT
tion of these two features enables phase shifts of 45° up
to 315° (Figure 14).
18
–
signals by serially programming mode control
–
, independently of the phase shift. The combina-
D0-D13, OF
CLKOUT
ENC
+
+
+
can be used to latch the
+
. To allow adequate
Figure 14. Phase-Shifting CLKOUT
+
/CLK-
+
and
+
+
,
DATA FORMAT
Table 1 shows the relationship between the analog input
voltage and the digital data output bits. By default the
output data format is offset binary. The 2’s complement
format can be selected by serially programming mode
control register A4. Note that when the analog input is
outside the normal operating range the two LSBs (D1,
D0) can change and should be ignored.
Table 1. Output Codes vs Input Voltage
Note: X means data could be 1 or 0.
225916 F14
< –1.000000V
>1.000000V
+0.999970V
+0.999939V
+0.999909V
+0.999978V
+0.000030V
+0.000000V
+0.000030V
+0.000061V
–0.999878V
–0.999909V
–0.999939V
–1.000000V
(2V Range)
A
PHASE
SHIFT
135°
180°
225°
270°
315°
IN
45°
90°
0°
+
– A
IN
CLKINV
–
0
0
0
0
1
1
1
1
MODE CONTROL BITS
1111 1111 1111 11XX
0000 0000 0000 00XX
1111 1111 1111 1111
1111 1111 1111 1110
1111 1111 1111 1101
1111 1111 1111 1100
1000 0000 0000 0001
1000 0000 0000 0000
0111 1111 1111 1111
0111 1111 1111 1110
0000 0000 0000 0011
0000 0000 0000 0010
0000 0000 0000 0001
0000 0000 0000 0000
(OFFSET BINARY)
CLKPHASE1
0
0
1
1
0
0
1
1
D15-D0
CLKPHASE0
0
1
0
1
0
1
0
1
0111 1111 1111 11XX
1000 0000 0000 00XX
0111 1111 1111 1111
0111 1111 1111 1110
0111 1111 1111 1101
0111 1111 1111 1100
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1110
1000 0000 0000 0011
1000 0000 0000 0010
1000 0000 0000 0001
1000 0000 0000 0000
(2’s COMPLEMENT)
D15-D0
225916f