AD7715ANZ-3 Analog Devices Inc, AD7715ANZ-3 Datasheet - Page 14

• Manufacturer Part Number: AD7715ANZ-3
• Description: IC ADC 16BIT SIGMA-DELTA 16DIP
• Manufacturer: Analog Devices Inc

Specifications of AD7715ANZ-3

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 16
• Sampling Rate (per Second): 500
• Number Of Converters: 1
• Power Dissipation (max): 9.5mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• Resolution (bits): 16bit
• Input Channel Type: Differential
• Supply Voltage Range - Analogue: 3V To 3.6V
• Supply Voltage Range - Digital: 3V To 5.25V
• Supply Current: 600µA
• No. Of: RoHS Compliant
• Sampling Rate: 19.2kSPS
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7715-3EBZ - BOARD EVALUATION FOR AD7715
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7715
CALIBRATION SEQUENCES
The AD7715 contains a number of calibration options as outlined previously. Table XIII summarizes the calibration types, the op-
erations involved and the duration of the operations. There are two methods of determining the end of calibration. The first is to
monitor when DRDY returns low at the end of the sequence. DRDY not only indicates when the sequence is complete but also that
the part has a valid new sample in its data register. This valid new sample is the result of a normal conversion which follows the cali-
bration sequence. The second method of determining when calibration is complete is to monitor the MD1 and MD0 bits of the
Setup Register. When these bits return to 0, 0 following a calibration command, it indicates that the calibration sequence is com-
plete. This method does not give any indication of there being a valid new result in the data register. However, it gives an earlier
indication than DRDY that calibration is complete. The duration to when the Mode Bits (MD1 and MD0) return to 0, 0 represents
the duration of the calibration carried out. The sequence to when DRDY goes low also includes a normal conversion and a pipeline
delay, t
in the table.
Calibration Type
Self Calibration
ZS System Calibration
FS System Calibration
CIRCUIT DESCRIPTION
The AD7715 is a sigma-delta A/D converter with on-chip digital
filtering, intended for the measurement of wide dynamic range,
low frequency signals such as those in industrial control or pro-
cess control applications. It contains a sigma-delta (or charge-
balancing) ADC, a calibration microcontroller with on-chip
static RAM, a clock oscillator, a digital filter and a bidirectional
serial communications port. The part consumes only 450 A of
power supply current, making it ideal for battery-powered or
loop-powered instruments. The part comes in two versions, the
AD7715-5 which is specified for operation from a nominal
+5 V analog supply (AV
fied for operation from a nominal +3.3 V analog supply. Both
versions can be operated with a digital supply (DV
+3.3 V or +5 V.
The part contains a programmable-gain fully differential analog
input channel. The selectable gains on this input are 1, 2, 32
and 128 allowing the part to accept unipolar signals of between
0 mV to +20 mV and 0 V to +2.5 V or bipolar signals in the
range from 20 mV to 2.5 V when the reference input voltage
equals +2.5 V. With a reference voltage of +1.25 V, the input
ranges are from 0 mV to +10 mV to 0 V to +1.25 V in unipolar
mode and from 10 mV to 1.25 V in bipolar mode. Note that
the bipolar ranges are with respect to AIN(–) and not with re-
spect to AGND.
The input signal to the analog input is continuously sampled at
a rate determined by the frequency of the master clock,
MCLK IN, and the selected gain. A charge-balancing A/D
converter (sigma-delta modulator) converts the sampled signal
into a digital pulse train whose duty cycle contains the digital
P
, to correctly scale the results of this first conversion. t
DD
) and the AD7715-3 which is speci-
MD1, MD0
0, 1
1, 0
1, 1
Calibration Sequence
Internal ZS Cal @ Selected Gain +
Internal FS Cal @ Selected Gain
ZS Cal on AIN @ Selected Gain
FS Cal on AIN @ Selected Gain
Table XIII. Calibration Sequences
DD
) voltage of
P
will never exceed 2000
–14–
information. The programmable gain function on the analog
input is also incorporated in this sigma-delta modulator with the
input sampling frequency being modified to give the higher
gains. A sinc
sigma-delta modulator and updates the output register at a rate
determined by the first notch frequency of this filter. The out-
put data can be read from the serial port randomly or periodi-
cally at any rate up to the output register update rate. The first
notch of this digital filter (and hence its –3 dB frequency) can be
programmed via the Setup Register bits FS0 and FS1. With a
master clock frequency of 2.4576 MHz, the programmable
range for this first notch frequency is from 50 Hz to 500 Hz
giving a programmable range for the –3 dB frequency of
13.1 Hz to 131 Hz. With a master clock frequency of 1 MHz,
the programmable range for this first notch frequency is from
20 Hz to 200 Hz giving a programmable range for the –3 dB
frequency of 5.24 Hz to 52.4 Hz.
The basic connection diagram for the AD7715-5 is shown in
Figure 2. This shows both the AV
AD7715 being driven from the analog +5 V supply. Some
applications will have AV
supplies. An AD780, precision +2.5 V reference, provides the
reference source for the part. On the digital side, the part is
configured for three-wire operation with CS tied to DGND. A
quartz crystal or ceramic resonator provides the master clock
source for the part. In most cases, it will be necessary to connect
capacitors on the crystal or resonator to ensure that it does
not oscillate at overtones of its fundamental operating fre-
quency. The values of capacitors will vary depending on the
manufacturer’s specifications.
Duration to Mode Bits
6
3
3
3
digital low-pass filter processes the output of the
1/Output Rate
1/Output Rate
1/Output Rate
t
CLK IN
DD
. The time for both methods is given
and DV
DD
DD
and DV
driven from separate
Duration to DRDY
9
4
4
1/Output Rate + t
1/Output Rate + t
1/Output Rate + t
DD
pins of the
REV. C
P
P
P