AD7661ASTZ Analog Devices Inc, AD7661ASTZ Datasheet - Page 21

• Manufacturer Part Number: AD7661ASTZ
• Description: IC ADC 16BIT W/REF 48-LQFP
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of AD7661ASTZ

• Data Interface: Serial, Parallel
• Number Of Bits: 16
• Sampling Rate (per Second): 100k
• Number Of Converters: 1
• Power Dissipation (max): 25mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Resolution (bits): 16bit
• Input Channel Type: Pseudo Differential
• Supply Voltage Range - Analogue: 4.75V To 5.25V
• Supply Voltage Range - Digital: 2.7V To 5.25V,
• Sampling Rate: 100kSPS
• Rohs Compliant: Yes
• Number Of Elements: 1
• Resolution: 16Bit
• Architecture: SAR
• Sample Rate: 100KSPS
• Input Polarity: Unipolar
• Input Type: Voltage
• Rated Input Volt: 2.5V
• Differential Input: Yes
• Power Supply Requirement: Analog and Digital
• Single Supply Voltage (typ): 5V
• Single Supply Voltage (min): 4.75V
• Single Supply Voltage (max): 5.25V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Power Dissipation: 45mW
• Differential Linearity Error: -1LSB/1.5LSB
• Integral Nonlinearity Error: ±2.5LSB
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Input Signal Type: Pseudo-Differential
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7661CBZ - BOARD EVALUATION FOR AD7661
• Lead Free Status / Rohs Status: Compliant

CONVERSION CONTROL
Figure 33 shows the detailed timing diagrams of the conversion
process. The AD7661 is controlled by the CNVST signal, which
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the conversion
is complete. CNVST operates independently of CS and RD .
Conversions can be automatically initiated with the AD7661. If
CNVST is held LOW when BUSY is LOW, the AD7661 controls
the acquisition phase and automatically initiates a new
conversion. By keeping CNVST LOW, the AD7661 keeps the
conversion process running by itself. It should be noted that the
analog input must be settled when BUSY goes LOW. Also, at
power-up, CNVST should be brought LOW once to initiate the
conversion process. In this mode, the AD7661 can run slightly
faster than the guaranteed 100 kSPS.
Although CNVST is a digital signal, it should be designed with
special care with fast, clean edges, and levels with minimum
overshoot and undershoot or ringing.
The CNVST trace should be shielded with ground and a low
value serial resistor (i.e., 50 Ω) termination should be added
close to the output of the component that drives this line.
For applications where SNR is critical, the CNVST signal should
have very low jitter. This may be achieved by using a dedicated
oscillator for CNVST generation, or to clock CNVST with a
high frequency, low jitter clock, as shown in Figure 26.
Rev. 0 | Page 21 of 28
CS = RD = 0
MODE
CNVST
CNVST
BUSY
RESET
CNVST
BUSY
BUSY
DATA
DATA
BUS
Figure 35. Master Parallel Data Timing for Reading (Continuous Read)
ACQUIRE
t
t
3
5
t
3
t
Figure 33. Basic Conversion Timing
PREVIOUS CONVERSION DATA
CONVERT
1
t
7
Figure 34. RESET Timing
t
4
t
t
1
9
t
2
t
6
t
10
ACQUIRE
t
t
4
8
t
8
t
11
AD7661
NEW DATA
CONVERT