AD7731BNZ Analog Devices Inc, AD7731BNZ Datasheet - Page 18

• Manufacturer Part Number: AD7731BNZ
• Description: IC ADC 24BIT SIGMA-DELTA 24DIP
• Manufacturer: Analog Devices Inc

Specifications of AD7731BNZ

• Data Interface: DSP, Serial, SPI™
• Number Of Bits: 24
• Sampling Rate (per Second): 6.4k
• Number Of Converters: 1
• Power Dissipation (max): 125mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 24-DIP (0.300", 7.62mm)
• Resolution (bits): 24bit
• Sampling Rate: 6.4kSPS
• Input Channel Type: Single Ended
• Supply Voltage Range - Analog: 4.75V To 5.25V
• Supply Voltage Range - Digital: 2.7V To 5.25V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7731EBZ - BOARD EVALUATION FOR AD7731
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD7731
Bit
Location
MR3
MR2–MR0
Filter Register (RS2-RS0 = 0, 1, 1); Power-On/Reset Status: 2002 Hex
The Filter Register is a 16-bit register from which data can either be read or to which data can be written. This register determines
the amount of averaging performed by the filter and the mode of operation of the filter. It also sets the chopping mode. Table XIV
outlines the bit designations for the Filter Register. FR0 through FR15 indicate the bit location, FR denoting the bits are in the Filter
Register. FR15 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit.
Figure 5 shows a flowchart for reading from the registers on the AD7731 and Figure 6 shows a flowchart for writing to the registers
on the part.
Bit
Location
FR15–FR4
S
S
F
F
F
F
1
R
3
R
1
1
(
7
Bit
Mnemonic
BO
CH2–CH0
5
(
Bit
Mnemonic
SF11–SF0
) 0
) 0
S
S
F
F
F
F
1
R
2
R
0
1
6
(
4
(
) 0
) 0
Burnout Current Bit. A 1 in this bit activates the burnout currents. When active, the burnout
Channel Select. These three bits select a channel either for conversion or for access to cali-
Description
currents connect to the selected analog input pair, one source current to the AIN(+) input
and one sink current to the AIN(–) input. A 0 in this bit turns off the on-chip burnout
currents.
bration coefficients as outlined in Table XIII. There are three pairs of calibration registers on
the part. In fully differential mode, the part has three input channels so each channel has its
own pair of calibration registers. In pseudo-differential mode, the AD7731 has five input
channels with some of the input channel combinations sharing calibration registers. With
CH2, CH1 and CH0 at a logic 1, the part looks at the AIN6 input internally shorted to itself.
This can be used as a test method to evaluate the noise performance of the part with no ex-
ternal noise sources. In this mode, the AIN6 input should be connected to an external volt-
age within the allowable common-mode range for the part. The power-on/default status of
these bits is 1, 0, 0.
CH2
0
0
0
0
1
1
1
1
Description
Sinc
The 12 bits programmed to SF11 through SF0 sets the amount of averaging which the Sinc
filter performs. As a result, the number programmed to these 12 bits affects the –3 dB fre-
quency and output update rate from the part (see Filter Architecture section). The allowable
range for SF words depends on whether the part is operated with CHP on or off and SKIP
on or off. Table XV outlines the SF ranges for different setups.
S
S
F
F
F
F
3
R
9
1
R
Filter Selection Bits. The AD7731 contains two filters, a Sinc
1
(
5
(
3
) 0
CH1 CH0 AIN(+) AIN(–) Type
0
0
1
1
0
0
1
1
) 1
Table XIV. Filter Register
0
1
0
1
0
1
0
1
S
S
F
F
F
F
R
8
0
R
1
(
4
(
2
) 0
) 0
AIN1
AIN2
AIN3
AIN4
AIN1
AIN3
AIN5
AIN6
–18–
Table XIII. Channel Selection
Z
S
E
F
F
F
R
AIN6
AIN6
AIN6
AIN6
AIN2
AIN4
AIN6
AIN6
R
7
R
O
1
(
3
1
) 0
(
) 0
Pseudo Differential
Pseudo Differential
Pseudo Differential
Pseudo Differential
Fully Differential
Fully Differential
Fully Differential
Test Mode
C
S
F
H
F
F
R
6
R
P
1
(
2
(
0
) 0
) 0
S
S
K
F
F
F
P I
5
R
R
(
9
1
(
) 0
) 1
Calibration Register Pair
Register Pair 0
Register Pair 1
Register Pair 2
Register Pair 2
Register Pair 0
Register Pair 1
Register Pair 2
Register Pair 2
3
filter and an FIR filter.
F
S
A
F
F
F
S
4
R
R
T
8
(
0
) 0
(
) 0
REV. A
REV. 0
3