AD7730BRUZ Analog Devices Inc, AD7730BRUZ Datasheet - Page 7

• Manufacturer Part Number: AD7730BRUZ
• Description: IC ADC TRANSDUCER BRIDGE 24TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7730BRUZ

• Data Interface: DSP, Serial, SPI™
• Number Of Bits: 24
• Sampling Rate (per Second): 1.2k
• Number Of Converters: 1
• Power Dissipation (max): 125mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP (0.173", 4.40mm Width)
• Resolution (bits): 24bit
• Input Channel Type: Differential, Single Ended
• Supply Voltage Range - Analog: 4.75V To 5.25V
• Supply Voltage Range - Digital: 2.7V To 5.25V
• Number Of Elements: 1
• Resolution: 24Bit
• Architecture: Delta-Sigma
• Sample Rate: 1.2KSPS
• Input Polarity: Unipolar/Bipolar
• Input Type: Voltage
• Differential Input: Yes
• Power Supply Requirement: Analog and Digital
• Single Supply Voltage (typ): 5V
• Single Supply Voltage (min): 4.75V
• Single Supply Voltage (max): 5.25V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Power Dissipation: 125mW
• Integral Nonlinearity Error: 18ppm of FSR
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 24
• Package Type: TSSOP
• Input Signal Type: Differential
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7730LEBZ - BOARD EVALUATION FOR AD7730EVAL-AD7730EBZ - BOARD EVAL FOR AD7730
• Lead Free Status / Rohs Status: Compliant

Pin
No.
REV. A
ISOLATES THE SAMPLING CAPACITOR
1
2
ON-CHIP BEFORE BEING APPLIED TO
THE SAMPLING CAPACITOR OF THE
SIGMA-DELTA MODULATOR. THIS
CHARGING CURRENTS FROM THE
THE INPUT SIGNAL IS BUFFERED
ANALOG INPUT PINS.
Mnemonic
SCLK
MCLK IN
SEE PAGE 24
BUFFER
TO BE PERFORMED EXTERNAL TO THE PART
ANALOG
THE ANALOG INPUT TO THE PART CAN BE
CHOPPING IS INTERNALTO THE DEVICE. IN
PERFORMED. THE INPUT CHOPPING CAN
CHOPPING MODE, WITH AC EXCITATION
ENABLED, THE CHOPPING IS ASSUMED
AND NO INTERNAL INPUT CHOPPING IS
AC EXCITATION DISABLED, THE INPUT
CHOPPED. IN CHOPPING MODE, WITH
INPUT
BE DISABLED, IF DESIRED.
INPUT CHOPPING
SEE PAGE 26
Function
Serial Clock. Schmitt-Triggered Logic Input. An external serial clock is applied to this input to transfer serial
data to or from the AD7730. This serial clock can be a continuous clock with all data transmitted in a con-
tinuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted
to or from the AD7730 in smaller batches of data.
Master Clock signal for the device. This can be provided in the form of a crystal/resonator or external clock. A
crystal/resonator can be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin
can be driven with a CMOS-compatible clock and MCLK OUT left unconnected. The AD7730 is specified
with a clock input frequency of 4.9152 MHz while the AD7730L is specified with a clock input frequency of
2.4576 MHz.
CHOP
AROUND THE SIGMA-DELTA MODULATOR.
PGA + SIGMA-DELTA MODULATOR
THE PROGRAMMABLE GAIN CAPABILITY
THE MODULATOR PROVIDES A HIGH-
FREQUENCY 1-BIT DATA STREAM
OF THE PART IS INCORPORATED
TO THE DIGITAL FILTER.
SEE PAGE 26
BUFFER
THE FIRST STAGE OF THE DIGITAL FILTERING
ONLY FILTERING PERFORMED ON THE PART.
OF THIS FILTER CAN BE PROGRAMMED. IN
OUTPUT UPDATE RATE AND BANDWIDTH
ON THE PART IS THE SINC
SKIP MODE, THE SINC
Figure 3. Signal Processing Chain
SIGMA-DELTA
MODULATOR
PIN FUNCTION DESCRIPTIONS
MCLK OUT
AIN2(+)/D1
MCLK IN
PGA +
SINC
AIN1(+)
AIN1(–)
RESET
SEE PAGE 26
AGND
SCLK
SYNC
V
AV
PIN CONFIGURATION
POL
BIAS
3
DD
FILTER
EXCITATION IS ENABLED OR DISABLED,
10
12
11
3
1
2
3
4
5
6
7
8
9
THE OUTPUT OF THE FIRST STAGE
BE CHOPPED. IN CHOPPING MODE,
PERFORMED. THE CHOPPING CAN
OF FILTERING ON THE PART CAN
FILTER IS THE
REGARDLESS OF WHETHER AC
3
(Not to Scale)
FILTER. THE
SINC
THE OUTPUT CHOPPING IS
BE DISABLED, IF DESIRED.
OUTPUT CHOPPING
AD7730
TOP VIEW
–7–
3
SEE PAGE 26
FILTER
24
23
22
20
19
18
17
16
15
14
13
21
DGND
DV
DIN
DOUT
RDY
CS
STANDBY
ACX
ACX
REF IN(–)
REF IN(+)
AIN2(–)/D0
STAGE OF FILTERING ON THE PART. THE
SINC
IN SKIP MODE, THERE IS NO SECOND
DD
CHOP
3
PERFORMED ON THE PART.
FILTER IS THE ONLY FILTERING
SKIP MODE
SEE PAGE 29
STAGE FILTERING IS PERFORMED BY THE
WHEN FASTSTEP MODE IS ENABLED
AND A STEP CHANGE ON THE INPUT
HAS BEEN DETECTED, THE SECOND
FASTSTEP FILTER UNTIL THE FIR
FASTSTEP
FILTER HAS FULLY SETTLED.
FIR FILTER
FILTER
22-TAP
FASTSTEP FILTER
SKIP
SEE PAGE 29
AD7730/AD7730L
COEFFICIENTS BEFORE BEING PROVIDED
FILTER IS SCALED BY THE CALIBRATION
SECOND STAGE OF THE DIGITAL FILTERING
DETECTED, THE SECOND STAGE FILTERING
THE OUTPUT WORD FROM THE DIGITAL
FILTER. IN SKIP MODE, THIS FIR FILTER IS
BYPASSED. WHEN FASTSTEP™ MODE IS
ON THE PART IS A FIXED 22-TAP FIR
IN NORMAL OPERATING MODE, THE
UNTIL THE OUTPUT OF THIS FILTER
AS THE CONVERSION RESULT.
ENABLED AND A STEP INPUT IS
IS PERFORMED BY THE FILTER
OUTPUT SCALING
22-TAP FIR FILTER
HAS FULLY SETTLED.
SCALING
OUTPUT
SEE PAGE 29
SEE PAGE 27
DIGITAL
OUTPUT