AD7686BRMZ Analog Devices Inc, AD7686BRMZ Datasheet - Page 20

• Manufacturer Part Number: AD7686BRMZ
• Description: IC ADC 16BIT 500KSPS 10-MSOP
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of AD7686BRMZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 16
• Sampling Rate (per Second): 500k
• Number Of Converters: 1
• Power Dissipation (max): 21.5mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP (0.118", 3.00mm Width)
• Resolution (bits): 16bit
• Input Channel Type: Pseudo Differential
• Supply Voltage Range - Analogue: 4.5V To 5.5V
• Supply Voltage Range - Digital: 1.8V To 5.8V, 2.3V To 5.8V
• Sampling Rate: 500kSPS
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7686CBZ - BOARD EVALUATION FOR AD7686
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD7686
CS MODE 4-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7686 is connected
to an SPI-compatible digital host, which has an interrupt input,
and it is desired to keep CNV, which is used to sample the
analog input, independent of the signal used to select the data
reading. This requirement is particularly important in
applications where low jitter on CNV is desired.
The connection diagram is shown in Figure 39 and the
corresponding timing is given in Figure 40.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI could
be used to select other SPI devices, such as analog multiplexers,
but SDI must be returned low before the minimum conversion
time and held low until the maximum conversion time to
guarantee the generation of the BUSY signal indicator. When
the conversion is complete, SDO goes from high impedance to
low. With a pull-up on the SDO line, this transition can be used
as an interrupt signal to initiate the data readback controlled by
ACQUISITION
SDO
CNV
SCK
SDI
t
SSDICNV
t
HSDICNV
CONVERSION
t
CONV
t
EN
Figure 40. CS Mode 4-Wire with BUSY Indicator Serial Interface Timing
1
t
t
HSDO
DSDO
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D15
2
t
CYC
the digital host. The AD7686 then enters the acquisition phase
and powers down. The data bits are then clocked out, MSB first,
by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate provided it has an acceptable hold time. After the optional
17th SCK falling edge, or SDI going high, whichever is earlier,
the SDO returns to high impedance.
D14
3
ACQUISITION
Figure 39. CS Mode 4-Wire with BUSY Indicator Connection Diagram
t
ACQ
t
SDI
SCKL
t
AD7686
SCKH
15
CNV
SCK
t
SCK
SDO
16
D1
VIO
17
D0
47kΩ
CLK
CS1
CONVERT
DATA IN
IRQ
t
DIGITAL HOST
DIS