AD7703AN Analog Devices Inc, AD7703AN Datasheet - Page 12

• Manufacturer Part Number: AD7703AN
• Description: IC ADC 20BIT LC2MOS 20-DIP
• Manufacturer: Analog Devices Inc

Specifications of AD7703AN

• Rohs Status: RoHS non-compliant
• Number Of Bits: 20
• Sampling Rate (per Second): 4k
• Data Interface: Serial
• Number Of Converters: 1
• Power Dissipation (max): 37mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 20-DIP (0.300", 7.62mm)

AD7703
INPUT SIGNAL CONDITIONING
Reference voltages from 1 V to 3 V may be used with the AD7703,
with little degradation in performance. Input ranges that cannot
be accommodated by this range of reference voltages may be
achieved by input signal conditioning. This may take the form of
gain to accommodate a smaller signal range, or passive attenua-
tion to reduce a larger input voltage range.
Source Resistance
If passive attenuators are used in front of the AD7703, care must
be taken to ensure that the source impedance is sufficiently low.
The dc input resistance for the AD7703 is over 1 GW. In paral-
lel with this, there is a small dynamic load that varies with the
clock frequency (see Figure 14).
Each time the analog input is sampled, a 10 pF capacitor draws a
charge packet of maximum 1 pC (10 pF ¥ 100 mV) from the
analog source with a frequency f
CLKIN, this yields an average current draw of 16 nA. After
each sample, the AD7703 allows 62 clock periods for the input
voltage to settle. The equation that defines settling time is
where V
signal, R is the value of the input source resistance, and C is the
10 pF sample capacitor. The value of t is equal to 62/f
The following equation can be developed, which gives the maxi-
mum allowable source resistance, R
Provided the source resistance is less than this value, the analog
input will settle within the desired error band in the requisite 62
clock periods. Insufficient settling leads to offset errors. These
can be calibrated in system calibration schemes.
If a limit of 600 nV (0.25 LSB at 20 bits) is set for the maximum
offset voltage, then the maximum allowable source resistance is
125 kW from the above equation, assuming that there is no
external stray capacitance.
Figure 14. Equivalent Input Circuit and Input Attenuator
V
IN
O
R
R1
, is the final settled value, V
S MAX
(
R2
)
=
f
CLKIN
V
AGND
C
O
EXT
A
IN
=V
¥
(
IN
10
1G
[1– e
pF
CLKIN
)
S(MAX)
V
62
–t/RC
¥
IN
OS
ln
/256. For a 4.096 MHz
, is the value of the input
100mV
(
]
, for an error of V
100
mV V
/
AD7703
E
C
10pF
)
IN
CLKIN
E
:
.
–12–
An RC filter may be added in front of the AD7703 to reduce
high frequency noise. With an external capacitor added from
A
allowable source resistance:
The practical limit to the maximum value of source resistance is
thermal (Johnson) noise. A practical resistor may be modeled as
an ideal (noiseless) resistor in series with a noise voltage source
or in parallel with a noise current source:
where k is Boltzmann’s constant (1.38 ¥ 10
temperature in degrees Kelvin (°C + 273).
Active signal conditioning circuits such as op amps generally do
not suffer from problems of high source impedance. Their open-
loop output resistance is normally only tens of ohms and, in any
case, most modern general-purpose op amps have sufficiently fast
closed-loop settling time for this not to be a problem. Offset volt-
age in op amps can be eliminated in a system calibration routine.
Antialias Considerations
The digital filter of the AD7703 does not provide any rejection
at integer multiples of the sampling frequency (nf
where n = 1, 2, 3 . . . ).
With a 4.096 MHz master clock, there are narrow (±10 Hz)
bands at 16 kHz, 32 kHz, 48 kHz, and so on, where noise passes
unattenuated to the output.
However, due to the AD7703’s high oversampling ratio of 800
(16 kHz to 20 Hz), these bands occupy only a small fraction of
the spectrum, and most broadband noise is filtered.
The reduction in broadband noise is given by
where e
the filter –3 dB corner frequency (f
sampling frequency (f
Since the ratio of f
broadband white noise by 96.5% independent of the master
clock frequency.
IN
R
S MAX
to AGND, the following equation will specify the maximum
(
in
)
and e
=
f
CLKIN
out
e
are rms noise terms referred to the input, f
out
¥
S
(
i
to f
n
C
=
CLKIN
V
IN
= 4
e
CLKIN
n
in
+
= 4
C
/256).
2
kTf R Amperes
EXT
f
is fixed, the digital filter reduces
C
kTRf Volts
)
/
/
f
¥
S
ln
CLKIN
62
=
È
Í
Í
Í
Í
Î
100
0 035
.
/409600), and f
mV
–23
e
in
¥
V
(
J/K), and T is
C
CLKIN
E
IN
C
+
IN
/256,
C
S
REV. E
EXT
is the
C
)
˘
˙
˙
˙
˙
˚
is