AD9262BCPZ-10 Analog Devices Inc, AD9262BCPZ-10 Datasheet
AD9262BCPZ-10
Specifications of AD9262BCPZ-10
Related parts for AD9262BCPZ-10
AD9262BCPZ-10 Summary of contents
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FEATURES SNR (85 dBFS MHz input SFDR: −87 dBc to 10 MHz input Noise figure Input impedance: 1 kΩ Power: 600 mW 1.8 V analog supply operation 1 3.3 V output supply ...
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... ESD Caution .................................................................................. 8 Pin Configuration and Function Descriptions ............................. 9 Typical Performance Characteristics ........................................... 10 AD9262BCPZ ............................................................................. 10 AD9262BCPZ-5 .......................................................................... 11 REVISION HISTORY 2/10—Rev Rev. A Changes to Figure 61 ...................................................................... 28 1/10—Revision 0: Initial Version AD9262BCPZ-10 ....................................................................... 12 Equivalent Circuits ......................................................................... 15 Theory of Operation ...................................................................... 16 Analog Input Considerations ................................................... 16 Clock Input Considerations ...................................................... 18 ...
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... Rev Page AD9262 1 = −2.0 dBFS, AD9262BCPZ-10 Max Min Typ Max Unit 16 Bits 10 MHz Guaranteed ±0.2 ±0.025 ±0.2 % FSR ±3.0 ±0.7 ±3.0 % FSR ±1.5 LSB ±0.2 ±0.035 ±0.2 % FSR ±1.3 ± ...
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... Data guaranteed over the full temperature range for the AD9262BCPZ-5 only. 4 Data guaranteed over the full temperature range for the AD9262BCPZ-10 only. 5 Noise figure with respect to 50 Ω. AD9262 internal impedance is 1000 Ω differential. See the AN-835 Application Note for a definition. ...
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... See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. AD9262BCPZ-5 Max Min Typ 3.75 5 <0 6.5 MHz − − >85 Rev Page AD9262 AD9262BCPZ-10 Max Min Typ Max 6 <0.1 13 MHz f /2 − S >85 Unit MHz dB ...
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AD9262 DIGITAL SPECIFICATIONS All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN = −2.0 dBFS, unless otherwise noted. Table 4. 1 Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, ...
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... See the AN-83 5 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Data skew is measured from DCO 50% transition to data (D0x to D15x) 50% transition, with 5 pF load. 3 Typical measured value for the AD9262BCPZ-10. For the AD9262BCPZ-5 and the AD9262BCPZ, typical values double and quadruple the number of cycles, respectively. 4 Cycles refers to modulator clock cycles. 5 Wake-up time is dependent on the value of the decoupling capacitor, value shown with 10uF capacitor on VREF and CFILT ...
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AD9262 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Electrical AVDD to AGND DVDD to DGND DRVDD to DGND AGND to DGND AVDD to DRVDD CVDD to CGND CGND to DGND D0A to D15A to DGND D0B to D15B to DGND DCO ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NOTES 1. THE EXPOSED PAD MUST BE SOLDERED TO THE GROUND PLANE FOR THE LFCSP PACKAGE. SOLDERING THE EXPOSED PADDLE TO THE PCB INCREASES THE RELIABILITY OF THE SOLDER JOINTS, MAXIMIZING THE THERMAL CAPACITY OF ...
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... FREQUENCY (MHz) Figure 6. AD9262BCPZ Single-Tone FFT with f : 600kHz AT –2dBFS Figure 7. AD9262BCPZ Single-Tone SNR and SFDR vs. Input Amplitude = 600 kHz IN BANDWIDTH: 2.5MHz DATA RATE: 40MSPS f : 1.2MHz AT –2dBFS IN SNR: 87.7dB SFDR: 87.1dBc 1.2 MHz IN BANDWIDTH: 2.5MHz DATA RATE: 40MSPS f : 2.4MHz AT – ...
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... FREQUENCY (MHz) Figure 12. AD9262BCPZ-5 Single-Tone FFT with f BANDWIDTH: 5MHz DATA RATE: 40MSPS f : 1.2MHz AT –2dBFS IN SNR: 85.3dB SFDR: 87.1dBc 1.2 MHz Figure 13. AD9262BCPZ-5 Single-Tone SNR and SFDR vs. Input Amplitude with IN : 2.4MHz AT –2dBFS 2.4 MHz Figure 14. AD9262BCPZ-5 Two-Tone FFT with 4.2MHz AT –2dBFS IN 14 ...
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... Figure 18. AD9262BCPZ-10 Single-Tone FFT with f : 2.4MHz AT –2dBFS 2.4 MHz Figure 19. AD9262BCPZ-10 Two-Tone FFT with 4.2MHz AT –2dBFS 4.2 MHz Figure 20. AD9262BCPZ-10 Two-Tone FFT with f IN BANDWIDTH: 10MHz DATA RATE: 40MSPS f : 8.4MHz AT –2dBFS IN SNR: 82.6dB SFDR: 104.1dBc 8.4 MHz Figure 21. AD9262BCPZ-10 Two-Tone FFT with f IN Rev Page ...
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... SFDR (dBc SNR (dB 100 OUTPUT DATA RATE (MSPS) Figure 24. AD9262BCPZ-10 SNR/SFDR vs. Output Data Rate with f SNR (dB) –30 –20 –10 –30 –20 –10 Figure 26. AD9262BCPZ-10 SFDR/SNR vs. Temperature with f 120 140 160 180 = 2.4 MHz Figure 27. AD9262BCPZ-10 SNR vs. Input Common-Mode Voltage IN Rev Page ...
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... PLL DIVIDE RATIO Figure 28. AD9262BCPZ-10 Single-Tone SNR vs. PLL Divide Ratio 12.0 14.0 16.0 21.0 12.5 15.0 17.0 Rev Page 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 ...
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EQUIVALENT CIRCUITS 500Ω 2V p-p DIFFERENTIAL 1.8V CM 500Ω Figure 30. Equivalent Analog Input Circuit CVDD CLK+ 10kΩ 10kΩ 90kΩ 30kΩ CVDD Figure 31. Equivalent Clock Input Circuit DRVDD 1kΩ SDIO Figure 32. Equivalent SDIO Input Circuit 1kΩ SCLK 30kΩ ...
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AD9262 THEORY OF OPERATION The AD9262 uses a continuous time Σ-Δ modulator to convert the analog input to a digital word. The digital word is processed by the decimation filter and rate-adjusted by the sample rate converter (see Figure 37). ...
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Input Common Mode The analog inputs of the AD9262 are not internally dc biased. In ac-coupled applications, the user must provide this bias externally. Setting the device such that V = AVDD is recommended for CM optimum performance. The analog ...
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AD9262 External Reference Operation If an external reference is desired, the internal reference can be disabled by setting Serial Register 0x18[6] high. Figure 49 shows an application using the ADR130B as a stable external reference. 0.5V ADR130B AVDD 0.1µF 10µF ...
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Internal PLL Clock Distribution The alternative clocking option available on the AD9262 is to apply a low frequency reference clock and use the on-chip clock multip- lier to generate the high frequency f MOD architecture is shown in Figure 53. ...
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AD9262 Table 11. Common Modulator Clock Multiplication Factors CLK± 0x0A[5:0] f VCO (MHz) (PLLMULT) (MHz) 30.72 42 1290.24 39.3216 32 1258.29 52.00 25 1300.00 61.44 21 1290.24 76.80 17 1305.60 78.00 17 1326.00 78.6432 16 1258.29 89.60 15 1344.00 92.16 ...
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... Table 14. DEC4 Filter Coefficients Coefficient Number C0, C22 3 ) decimate-by-2 C1, C21 C2, C20 C3, C19 C4, C18 C5, C17 Table 15. LPF/EQZ Filter Coefficients Coefficient Number C0, C62 C1, C61 AD9262BCPZ-10 C2, C60 10 MHz C3, C59 5 MHz C4, C58 2.5 MHz C5, C57 2.5 MHz C6, C56 C7, C55 C8, C54 C9, C53 C10, C52 C11, C51 C12, C50 ...
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AD9262 Sample Rate Converter The sample rate converter (SRC) allows the flexibility of a user-defined output sample rate, enabling a more efficient and direct interface to the digital receiver blocks. The sample rate converter performs an interpolation and resampling procedure ...
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Cascaded Filter Responses The cascaded filter responses for the three signal bandwidth settings are for a 160 MSPS output data rate, as shown in Figure 55, Figure 56, and Figure 57. 0 0.08 –20 0.04 –40 0 –60 –0.04 –80 ...
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AD9262 110 OUTPUT DATA RATE (MSPS) Figure 58. DC Correction Low Frequency Notch Filter 3 dB Bandwidth vs. Output Data Rate In applications where constant tracking of the dc ...
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Table 20 shows the corresponding threshold level in dBFS vs. register setting. If the input signal crosses this level, the ORx pin is set. In the case where 0x111[5:0] is set to all 0s, the threshold level is set to ...
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AD9262 SERIAL PORT INTERFACE (SPI) The AD9262 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. This provides the user added flexibility and customization ...
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HARDWARE INTERFACE The pins described in Table 22 comprise the physical interface between the programming device of the user and the serial port of the AD9262. The SCLK and CSB pins function as inputs when using the SPI interface. The ...
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AD9262 APPLICATIONS INFORMATION FILTERING REQUIREMENT The need for antialias protection often requires one or two octaves for a transition band, which reduces the usable band- width of a Nyquist converter to between 25% and 50% of the available bandwidth. A ...
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Table 24. Chebyshev II Filter Components Parameter Value Unit Manufacturer Murata GRM188 series, 0603 L1 180 nH Coil Craft 0603 LS 390 pF Murata GRM188 series, 0603 C3 150 pF Murata GRM188 series, 0603 In ...
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AD9262 MEMORY MAP Table 25. Memory Map Register Name Address Bit 7 SPI Port Config 0x00 0 Chip ID 0x01 Chip Grade 0x02 Channel Index 0x05 Power Modes 0x08 PLLENABLE 0x09 PLL 0x0A PLLLOCKED Analog Input 0x0F Output Modes 0x14 ...
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Register Address Bit(s) Output Modes 0x14 [1:0] Output Adjust 0x15 [3:2] [1:0] Output Clock 0x16 7 Reference 0x18 6 Output Data 0x101 6 [5:0] Overrange 0x111 7 6 [5:0] QEC1 0x112 ...
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... INDICATOR 12° MAX 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE Model 1 Temperature Range AD9262BCPZ-10 −40°C to +85°C AD9262BCPZ-5 −40°C to +85°C AD9262BCPZ −40°C to +85°C AD9262EBZ AD9262-5EBZ AD9262-10EBZ RoHS Compliant Part. ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...