AD7870SQ Analog Devices Inc, AD7870SQ Datasheet - Page 15

• Manufacturer Part Number: AD7870SQ
• Description: IC ADC 12BIT SAMPLING 3V 24-CDIP
• Manufacturer: Analog Devices Inc

Specifications of AD7870SQ

• Rohs Status: RoHS non-compliant
• Number Of Bits: 12
• Sampling Rate (per Second): 100k
• Data Interface: Serial, Parallel
• Number Of Converters: 1
• Power Dissipation (max): 95mW
• Voltage Supply Source: Dual ±
• Operating Temperature: -55°C ~ 125°C
• Mounting Type: Through Hole
• Package / Case: 24-CDIP (0.300", 7.62mm)

The Mode 1 timing diagram for byte and serial data is shown
in Figure 15. INT goes low at the end of conversion and is reset
high by the first falling edge of CS and RD . This first read at the
end of conversion can either access the low byte or high byte of
data depending on the status of HBEN (
byte only for example). The diagram shows both a nonconti-
nuously and a continuously running clock (dashed line).
MODE 2 INTERFACE
The second interface mode is achieved by hard wiring
CONVST low and conversion is initiated by taking CS low
while HBEN is low. The track-and-hold amplifier goes into the
hold mode on the falling edge of CS . In this mode, the BUSY
/ INT pin assumes its BUSY function. BUSY goes low at the start
CONVST
1
2
3
SSTRB
SDATA
TIMES
EXTERNAL 4.7kΩ PULL-UP RESISTOR.
EXTERNAL 2kΩ PULL-UP RESISTOR;
HBEN
SCLK
CONTINUOUS SCLK (DASHED LINE) WHEN 12/8/CLK = –5V;
NONCONTINUOUS WHEN 12/8/CLK = 0V.
DATA
INT
RD
CS
1
2
3
2
t
2
,
t
3
,
t
4
,
t
t
8
1
, AND
t
10
t
9
ARE THE SAME FOR A HIGH BYTE READ AS FOR A LOW BYTE READ.
TRACK-AND-HOLD GOES INTO HOLD
CONVST
DATA
INT
THREE-STATE
RD
TRACK-AND-HOLD RETURNS TO TRACK
LEADING
CS
ZEROS
Figure 15
t
11
AND ACQUISITION TIME BEGINS
t
t
CONVERT
1
t
12
Figure 14. Mode 1 Timing Diagram, 12-Bit Parallel Read
Figure 15. Mode 1 Timing Diagram, Byte or Serial Read
shows low
THREE-STATE
DB11
TRACK-AND-HOLD
GOES INTO HOLD
TRACK-AND-HOLD RETURNS
ACQUISITION TIME BEGINS
DB10
SERIAL DATA
TO TRACK AND
t
Rev. C | Page 15 of 28
CONVERT
t
14
DB0
t
2
of conversion, stays low during the conversion and returns high
when the conversion is complete. It is normally used in parallel
interfaces to drive the microprocessor into a WAIT state for the
duration of conversion. Mode 2 is not relevant for the AD7870A
device.
Figure 16 shows the Mode 2 timing diagram for the 12-bit
parallel data output format (12/ 8 /CLK = +5 V). In this case, the
ADC behaves like slow memory. The major advantage of this
interface is that it allows the microprocessor to start conversion,
WAIT and then read data with a single READ instruction. The
user does not have to worry about servicing interrupts or
ensuring that software delays are long enough to avoid reading
during conversion.
t
t
8
5
t
t
13
2
t
t
t
5
6
4
t
DB7 TO DB0
3
VALID
DATA
DB11 TO DB0
t
3
VALID
DATA
t
t
9
7
t
7
t
4
t
4
AD7870/AD7875/AD7876
DB11 TO DB8
VALID
DATA