MAX1197ECM+TD Maxim Integrated Products, MAX1197ECM+TD Datasheet - Page 11

• Manufacturer Part Number: MAX1197ECM+TD
• Description: IC ADC 8BIT 60MSPS DL 48-TQFP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1197ECM+TD

• Number Of Bits: 8
• Sampling Rate (per Second): 60M
• Data Interface: Parallel
• Number Of Converters: 2
• Power Dissipation (max): 150mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 1. Pipelined Architecture—Stage Blocks
The MAX1197 uses a seven-stage, fully differential,
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consump-
tion. Samples taken at the inputs move progressively
through the pipeline stages every half-clock cycle.
Including the delay through the output latch, the total
clock-cycle latency is five clock cycles.
Flash ADCs convert the held input voltages into a digi-
tal code. Internal MDACs convert the digitized results
V
INA
T/H
PIN
42
43
44
45
46
47
48
Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with
STAGE 1
REFOUT
______________________________________________________________________________________
NAME
REFIN
DIGITAL ALIGNMENT LOGIC
REFN
Internal Reference and Parallel Outputs
REFP
D5A
D6A
D7A
Detailed Description
V
V
D7A–D0A
STAGE 2
INA
INB
= INPUT VOLTAGE BETWEEN INA+ AND INA- (DIFFERENTIAL OR SINGLE ENDED)
= INPUT VOLTAGE BETWEEN INB+ AND INB- (DIFFERENTIAL OR SINGLE ENDED)
8
Three-State Digital Output, Bit 5, Channel A
Three-State Digital Output, Bit 6, Channel A
Three-State Digital Output, Bit 7 (MSB), Channel A
Internal Reference Voltage Output. May be connected to REFIN through a resistor or a resistor
divider.
Reference Input. V
Bypass to GND with a > 0.1µF capacitor.
Positive Reference I/O. Conversion range is ±(V
Bypass to GND with a > 0.1µF capacitor.
Negative Reference I/O. Conversion range is ±(V
Bypass to GND with a > 0.1µF capacitor.
STAGE 6
REFIN
2-BIT FLASH
STAGE 7
ADC
= 2 x (V
REFP
back into analog voltages, which are then subtracted
from the original held input signals. The resulting error
signals are then multiplied by two, and the residues are
passed along to the next pipeline stages where the
process is repeated until the signals have been
processed by all seven stages.
Figure 2 displays a simplified functional diagram of the
input T/H circuits in both track and hold mode. In track
mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b
V
– V
INB
T/H
REFN
FUNCTION
).
STAGE 1
REFP
REFP
Pin Description (continued)
– V
– V
DIGITAL ALIGNMENT LOGIC
REFN
Input Track-and-Hold Circuits
REFN
D7B–D0B
).
STAGE 2
).
8
STAGE 6
2-BIT FLASH
STAGE 7
ADC
11