MAX1197ECM+TD Maxim Integrated Products, MAX1197ECM+TD Datasheet - Page 14

• Manufacturer Part Number: MAX1197ECM+TD
• Description: IC ADC 8BIT 60MSPS DL 48-TQFP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1197ECM+TD

• Number Of Bits: 8
• Sampling Rate (per Second): 60M
• Data Interface: Parallel
• Number Of Converters: 2
• Power Dissipation (max): 150mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
Figure 4. Output Timing Diagram
applications. The clock input should always be consid-
ered as an analog input and routed away from any ana-
log input or other digital signal lines.
The MAX1197 clock input operates with a voltage thresh-
old set to V
than 50% must meet the specifications for high and low
periods as stated in the Electrical Characteristics table.
Figure 3 depicts the relationship between the clock
input, analog input, and data output. The MAX1197
samples at the rising edge of the input clock. Output
data for channels A and B is valid on the next rising
edge of the input clock. The output data has an internal
latency of five clock cycles. Figure 3 also determines
the relationship between the input clock parameters
and the valid output data on channels A and B.
All digital outputs, D0A–D7A (channel A) and D0B–D7B
(channel B), are TTL/CMOS-logic compatible. There is a
five-clock-cycle latency between any particular sample
and its corresponding output data. The output coding
can either be straight offset binary or two’s complement
(Table 1) controlled by a single pin (T/B). Pull T/B low to
select offset binary and high to activate two’s comple-
ment output coding. The capacitive load on the digital
outputs D0A–D7A and D0B–D7B should be kept as low
as possible (<15pF), to avoid large digital currents that
could feed back into the analog portion of the MAX1197,
thereby degrading its dynamic performance. Using
14
where f
t
Clock jitter is especially critical for undersampling
AJ
Digital Output Data (D0A/B–D7A/B), Output
D7A–D0A
D7B–D0B
OUTPUT
OUTPUT
is the time of the aperture jitter.
______________________________________________________________________________________
OE
IN
Data Format Selection (T/B), Output
SNR
represents the analog input frequency and
DD
HIGH-Z
HIGH-Z
/2. Clock inputs with a duty cycle other
=
System Timing Requirements
t
ENABLE
20
×
log
2
×
VALID DATA
VALID DATA
π
t
DISABLE
×
1
f
IN
×
Enable (OE)
t
AJ
HIGH-Z
HIGH-Z
Table 1. MAX1197 Output Codes For
Differential Inputs
*V
buffers on the digital outputs of the ADCs can further
isolate the digital outputs from heavy capacitive loads.
To further improve the dynamic performance of the
MAX1197, small series resistors (e.g., 100Ω) may be
added to the digital output paths close to the MAX1197.
Figure 4 displays the timing relationship between out-
put enable and data output valid, as well as power-
down/wake-up and data output valid.
The MAX1197 offers two power-save modes—sleep
mode (SLEEP) and full power-down (PD) mode. In
sleep mode (SLEEP = 1), only the reference bias circuit
is active (both ADCs are disabled), and current con-
sumption is reduced to 3mA.
To enter full power-down mode, pull PD high. With OE
simultaneously low, all outputs are latched at the last
value prior to the power down. Pulling OE high forces
the digital outputs into a high-impedance state.
Figure 5 depicts a typical application circuit containing
two single-ended-to-differential converters. The internal
reference provides a V
shifting purposes. The input is buffered and then split
to a voltage follower and inverter. One lowpass filter per
amplifier suppresses some of the wideband noise
associated with high-speed operational amplifiers. The
user can select the R
filter performance, to suit a particular application. For
the application in Figure 5, a R
before the capacitive load to prevent ringing and oscil-
-V
-V
V
D IFF ER EN T IAL
REF
-V
V
REF
REF
REF
VO LT A G E*
REF
REF
IN PU T
= V
x 255/256
x 255/256
x 256/256
x 1/256
0
x 1/256
REFP
- V
REFN
Applications Information
D IFF ER EN T IAL
Power-Down and Sleep Modes
Bipolar zero
+Full Scale
-Full Scale
-Full Scale
+1LSB
+1LSB
IN PU T
-1LSB
-1LSB
ISO
DD
and C
/2 output voltage for level-
ST RA IG HT
1111 1111
1000 0001
1000 0000
0111 1111
0000 0001
0000 0000
IN
O F FSET
B INA R Y
T/B = 0
ISO
values to optimize the
of 50Ω is placed
C O M PL EM EN T
0111 1111
0000 0001
0000 0000
1111 1111
1000 0001
1000 0000
T/B = 1
T WO’S