CS5520-BSZ Cirrus Logic Inc, CS5520-BSZ Datasheet - Page 18

• Manufacturer Part Number: CS5520-BSZ
• Description: IC ADC 20BIT BRIDGE TRAS 24-SOIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5520-BSZ

• Number Of Bits: 20
• Sampling Rate (per Second): 60
• Data Interface: Serial
• Number Of Converters: 2
• Power Dissipation (max): 37.5mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1102-5

18
AIN and VREF Non-Ratiometric Offset Registers
DAC Register
Note: 1. Reset State
AIN Ratiometric Offset Register
GAIN Register
18
Register
Reset (R)
Register
Reset (R)
Register
Reset (R)
DAC3
DAC2-0
Bits
D19 to D0
Register
Reset (R)
Register
Reset (R)
BIT
One LSB represents 2
2. A write to these bits does not change the register bit values.
One LSB represents 2
The gain register span from 0 to (2-2
DAC Sign Bit
DAC Bits
MSB
MSB
MSB
2
2
2
0
DAC3
0
1
0
0
0
A/S
D23
D11
0
0
NAME
2
2
2
-1
0
DAC2
-1
0
-1
0
-23
-23
D22
D10
EC
0
0
proportion of the internal MDRV ( 2.5 Volts)
proportion of the voltage [<(VREF+) - (VREF-)>/GAIN] where GAIN = 25 X PGA Gain
2
2
2
-2
0
-2
0
-2
0
DAC1
D21
D9
D9
0
0
-23
2
2
2
-3
0
DAC0
000
001
010
011
100
101
110
111
-3
0
-3
0
). After Reset the MSB=1, all other bits are 0.
Table 4. Calibration Registers
0
1
0
D20
D8
D8
VALUE
0
0
2
2
2
-4
0
-4
0
-4
0
EXC
CC3
D19
D7
R
R
R
0
0
1
2
2
2
0
0
0
-5
-5
-5
CC2
D18
Add Offset
Subtract Offset
25% Offset
50% Offset
75% Offset
100% Offset
125% Offset
150% Offset
175% Offset
These bits mirror the
Configuration Register
F1
D6
0
0
CC1
2
2
2
D17
F0
D5
-18
-18
-18
0
0
0
0
0
CC0
D16
2
2
2
D16
D4
-19
-19
-19
0
0
0
0
0
FUNCTION
2
2
2
D15
G1
D3
D3
-20
-20
-20
0
0
0
read only
0
0
CS5516, CS5520
2
2
2
D14
G0
D2
D2
-21
-21
-21
2
0
0
0
0
0
2
U/B
2
2
D13
D1
D1
-22
-22
-22
0
0
0
0
0
DS74F2
DS74F1
D12
2
2
2
LSB
LSB
LSB
D12
RF
D0
-23
-23
-23
0
0
0
0
0