CS5520-BSZ Cirrus Logic Inc, CS5520-BSZ Datasheet - Page 19

• Manufacturer Part Number: CS5520-BSZ
• Description: IC ADC 20BIT BRIDGE TRAS 24-SOIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5520-BSZ

• Number Of Bits: 20
• Sampling Rate (per Second): 60
• Data Interface: Serial
• Number Of Converters: 2
• Power Dissipation (max): 37.5mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1102-5

Reading a register in the converter requires a
command word to be written to the SID pin.
For example, to read the conversion data regis-
ter, the following command sequence should be
performed. First, the command word 88(H)
would be issued to the port. In the 5 wire inter-
face mode, this would involve activating CS
low, followed by 8 SCLKs (note that SCLK
must always start low and transition from low to
high to latch the transmit data, and then back
low again) to input the 8-bit command word. CS
must be low for the serial port to recognize
SCLKs during a write or a read, but it is actually
the first rising SCLK during command time that
gives the user control over the port. After writ-
ing the command word, the user must pause and
wait until the CS5520 presents the selected reg-
ister data to the serial port. The DRDY signal
will fall when the data is available. When read-
ing the conversion data register, it may take up
to 112,000 XIN clock cycles for DRDY to fall
after the 88(H) command word is recognized.
See Figure 4 for an illustration of command and
data word timing.
The conversion data register is actually the accu-
mulator of the post-processor which computes
the output data. At the end of each filter convo-
lution cycle, the internal microcontroller checks
to see if a read conversion data register com-
mand has been interpreted. If so, it transfers the
accumulator result to the serial port.
Whenever registers other than the conversion
data register are read, the DRDY pin will fall
within 256 XIN clock cycles (62.5
XIN = 4.096 MHz) after the command word is
recognized. When DRDY falls, 24 SCLKs are
then issued to the port to read the 24-bit output
data word. DRDY will return high after all 24
bits have been clocked out. The SOD pin will be
in a Hi-Z state whenever CS is high, or after all
24 output data bits have been clocked out of the
port.
DS74F1
DS74F2
s with
The CS5516/20 is designed such that it can out-
put conversion data words continuously, without
issuing a new command word prior to each data
read. Under the following circumstances, con-
tinuous conversion data can be read from the
port after issuing only one 88(H) command
word. Once the command to read the conversion
data register is issued, DRDY must be allowed
to go low, after which 24 SCLKs are issued to
read the data. This will cause DRDY to return
high.
The converter will continue to output conversion
words at the update rate as long as a different
command word is not started prior to DRDY
falling again. The user is not required to read
every output word to remain in the continuous
update mode. DRDY will toggle high, and then
low as each new output word becomes available.
If a command word is issued immediately after a
data word is read, the converter will end the read
conversion mode. Figure 5 illustrates the con-
tinuous data mode.
The user should perform all data reads and com-
mand writes within 51,000 XIN clock cycles
after DRDY falls to avoid ambiguity as to who
controls the serial port.
If SMODE = 1 (tied to VD+), the interface oper-
ates as a 3 wire interface using only SOD, SID,
and SCLK. In the 3 wire mode CS must be tied
to DGND. DRDY operates normally but is not
used. Instead, the DRDY signal modifies the
behavior of the SOD signal, allowing it to signal
to the user when data is available. To read data
from the converter requires a command word to
be written to the SID pin. The SOD output is
normally high (never Hi-Z). When output data
is available, the SOD signal will go low. The
user would then issue 8 SCLKs to the SCLK pin
to clear this data ready signal. On the falling
edge of the 8th SCLK the SOD pin will present
the first bit of the 24-bit output word. 24 SCLKs
are then issued to read the data. Then SOD will
go high. SID should remain low whenever the
CS5516, CS5520
19
19