AD7453ART-REEL7 Analog Devices Inc, AD7453ART-REEL7 Datasheet - Page 14

• Manufacturer Part Number: AD7453ART-REEL7
• Description: IC ADC 12BIT DFF 600KSPS SOT23-8
• Manufacturer: Analog Devices Inc

Specifications of AD7453ART-REEL7

• Design Resources: Measuring -48 V High-Side Current Using AD629, AD8603, AD780, and AD7453 (CN0100)
• Number Of Bits: 12
• Sampling Rate (per Second): 555k
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 7.25mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: SOT-23-8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD7453
Sixteen serial clock cycles are required to perform a conversion
and to access data from the AD7453. CS going low provides the
first leading zero to be read in by the microcontroller or DSP.
The remaining data is then clocked out on the subsequent
SCLK falling edges, beginning with the second leading zero.
Thus the first falling clock edge on the serial clock provides the
second leading zero. The final bit in the data transfer is valid on
the 16
(15
has been accessed after the 16 clock cycles, it is important to
ensure that, before the next conversion is initiated, enough time
is left to meet the acquisition and quiet time specifications. See
Timing Example 1.
In applications with a slower SCLK, it may be possible to read in
data on each SCLK rising edge, i.e., the first rising edge of SCLK
after the CS falling edge would have the leading zero provided,
and the 15
th
) falling edge. Once the conversion is complete and the data
th
falling edge, having been clocked out on the previous
th
SCLK edge would have DB0 provided.
SCLK
CS
t
10ns
2
1
2
3
12.5(1/F
Figure 23. Serial Interface Timing Example
4
SCLK
t
5
)
Rev. B | Page 14 of 20
5
t
CONVERT
1/THROUGHPUT
Timing Example 1
Having F
a cycle time of
A cycle consists of
Therefore if t
This 540 ns satisfies the requirement of 290 ns for t
Figure 23, t
where t
satisfying the minimum requirement of 60 ns.
13
8
= 35 ns. This allows a value of 255 ns for t
SCLK
14
t
ACQ
6
10 ns + 12.5(1/10 MHz) + t
= 10 MHz and a throughput rate of 555 kSPS gives
2
= 10 ns,
comprises
1/Throughput = 1/555,000 = 1.8 µs
t
2
15
+ 12.5(1/F
t
ACQUISITION
2.5(1/F
t
8
t
ACQ
16
SCLK
SCLK
= 540 ns
) + t
) + t
t
QUIET
8
ACQ
+ t
QUIET
= 1.8 µs
ACQ
= 1.8 µs
QUIET
ACQ
. From
,