ADC1175-50CIJMX National Semiconductor, ADC1175-50CIJMX Datasheet - Page 12

• Manufacturer Part Number: ADC1175-50CIJMX
• Description: IC ADC 8BIT SOP-24
• Manufacturer: National Semiconductor

Specifications of ADC1175-50CIJMX

• Number Of Bits: 8
• Sampling Rate (per Second): 50M
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 125mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -20°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.200", 5.30mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *ADC1175-50CIJMX

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Functional Description
The ADC1175-50 maintains superior dynamic performance
with input frequencies up to 1/2 the clock frequency, achieving
6.8 effective bits with a 50 MHz sampling rate and 25 MHz
input frequency.
The analog signal at V
by V
Input voltages below V
of all zeroes. Input voltages above V
word to consist of all ones. While the ADC1175-50 is specified
for top and bottom reference voltages (V
and 0.6V, respectively, and will give best performance at
these values, V
voltage, AV
should always be at least 1.0V more positive than V
V
frequency to maintain SINAD performance. V
ways be between 1.0V and 2.8V more positive than V
If V
connected together, the nominal values of V
2.6V and 0.6V, respectively. If V
together and V
2.3V.
Data is acquired at the falling edge of the clock and the digital
equivalent of that data is available at the digital outputs 2.5
clock cycles plus t
long as the clock signal is present at the CLK pin. The PD pin,
when high, puts the device into the Power Down mode. When
the PD pin is low, the device is in the normal operating mode.
The Power Down pin (PD), when high, puts the ADC1175-50
into a power down mode where power consumption is typi-
RT
RT
voltages above 2.8V, it is necessary to reduce the clock
RT
and V
and V
RTS
DD
RB
, while V
RB
are connected together and V
RT
are digitized to eight bits at up to 55 MSPS.
OD
has a range of 1.0V to the analog supply
is grounded, the nominal value of V
later. The ADC1175-50 will convert as
RB
IN
RB
will cause the output word to consist
that is within the voltage range set
has a range of 0V to 4.0V. V
RT
and V
RT
will cause the output
RT
RTS
and V
RB
RT
are connected
RT
and V
and V
RB
should al-
) or 2.6V
RB
RBS
RB
RB
. With
RT
.
are
are
RT
is
12
cally less than 5 mW. When the part is powered down, the
digital output pins are in a high impedance TRI-STATE. It
takes about 140 ns for the part to become active upon coming
out of the power down mode.
Applications Information
(All Schematic pin numbers refer to the TSSOP.)
1.0 THE ANALOG INPUT
The analog input of the ADC1175-50 is a switch followed by
an integrator. That is, a switched capacitor input, appearing
as 4 pF when the clock is low, and 7 pF when the clock is high.
Switched capacitor inputs produce voltage spikes at the input
pin at the ADC sample rate. There should be no attempt to
eliminate these spikes, but they should settle out during the
sample period (the clock high time). An RC at the ADC analog
input pin, as shown in Figure 3, will help. For Nyquist appli-
cations, the capacitor should be about 10 times ADC track
mode input capacitance and the pole frequency of this RC
should be about the ADC sample rate. The LMH6702, and the
LMH6609 have been found to be excellent amplifiers for driv-
ing the ADC1175-50. Do not drive the input beyond the supply
rails. Figure 3 shows an example of an input circuit using the
LMH6702.
Driving the analog input with input signals up to 2.8 V
result in normal behavior where signals above V
in a code of FFh and input voltages below V
output code of zero. Input signals above 2.8 V
in odd behavior where the output code is not FFh when the
input exceeds V
RT
.
RB
will result in an
P-P
RT
may result
will result
P-P
will