ADC1175-50CIJMX National Semiconductor, ADC1175-50CIJMX Datasheet - Page 16

• Manufacturer Part Number: ADC1175-50CIJMX
• Description: IC ADC 8BIT SOP-24
• Manufacturer: National Semiconductor

Specifications of ADC1175-50CIJMX

• Number Of Bits: 8
• Sampling Rate (per Second): 50M
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 125mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -20°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.200", 5.30mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *ADC1175-50CIJMX

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necessary to have sufficient capacitance between the power
and ground planes.
If separate analog and digital ground planes are used, the
analog and digital grounds may be in the same layer, but
should be separated from each other. If separate analog and
digital ground layers are used, they should never overlap
each other.
Capacitive coupling between a typically noisy digital ground
plane and the sensitive analog circuitry can lead to poor per-
formance that may seem impossible to isolate and remedy.
The solution is to keep the analog circuitry well separated
from the digital circuitry.
Digital circuits create substantial supply and ground current
transients. The logic noise thus generated could have signif-
icant impact upon system noise performance. The best logic
family to use in systems with A/D converters is one which
employs non-saturating transistor designs, or has low noise
characteristics, such as the 74LS and the 74HC(T) families.
The worst noise generators are logic families that draw the
largest supply current transients during clock or signal edges,
like the 74F family. In general, slower logic families will pro-
duce less high frequency noise than do high speed logic
families.
Since digital switching transients are composed largely of
high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise.
This is because of the skin effect. Total surface area is more
important than is total ground plane volume.
An effective way to control ground noise is by using a single,
solid ground plane and splitting the power plane into analog
and digital areas and to have power and ground planes in
adjacent board layers. There should be no traces within either
the power or the ground layers of the board. The analog and
digital power planes should reside in the same board layer so
that they can not overlap each other. The analog and digital
power planes define the analog and digital areas of the board.
Mount digital components and run digital lines only in the dig-
ital areas of the board. Mount the analog components and run
analog lines only in the analog areas of the board. Be sure to
treat all digital lines greater that one inch for each nanosecond
of rise time as transmission lines. That is, they should be of
constant, controlled impedance, be properly terminated at the
source end and run from one point to another single point.
The back of the LLP package has a large metal area inside
the area bounded by the pins. This metal area is connected
to the die substrate (ground). This pad may be left floating if
desired. If it is connected to anything, it should be to ground
near the connection between analog and digital ground
planes. Soldering this metal pad to ground will help keep the
die cooler and could yield improved performance because of
the lower impedance between die and board grounds. How-
ever, a poor layout could compromise performance.
Generally, analog and digital lines should cross each other at
90° to avoid getting digital noise into the analog path. In high
frequency systems, however, avoid crossing analog and dig-
ital lines altogether. Clock lines should be isolated from ALL
other lines, analog AND digital. Even the generally accepted
90° crossing should be avoided as even a little coupling can
cause problems at high frequencies. Best performance at
high frequencies and at high resolution is obtained with a
straight signal path.
Be especially careful with the layout of inductors. Mutual in-
ductance can change the characteristics of the circuit in which
they are used. Inductors should not be placed side by side
16
with each other, not even with just a small part of their bodies
beside each other.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. Any ex-
ternal component (e.g., a filter capacitor) connected between
the converter's input and ground should be connected to a
very clean point in the ground plane.
7.0 DYNAMIC PERFORMANCE
The ADC1175-50 is a.c. tested and its dynamic performance
is guaranteed. To meet the published specifications, the clock
source driving the CLK input must be free of jitter. For best
a.c. performance, isolating the ADC clock from any digital cir-
cuitry should be done with adequate buffers, as with a clock
tree. See Figure 6.
FIGURE 6. Isolating the ADC Clock from Digital Circuitry
It is good practice to keep the ADC clock line as short as pos-
sible and to keep it well away from any other signals. Other
signals can introduce jitter into the clock signal.
8.0 COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power
supply rails. For proper operation, all inputs should not go
more than 50 mV below the ground pins or 50 mV above the
supply pins. Exceeding these limits on even a transient basis
may cause faulty or erratic operation. It is not uncommon for
high speed digital circuits to exhibit undershoot that goes
more than a volt below ground due to improper termination.
A resistor of about 50Ω to 100Ω in series with the offending
digital input, located close to the signal source, will usually
eliminate the problem.
Care should be taken not to overdrive the inputs of the
ADC1175-50. Such practice may lead to conversion inaccu-
racies and even to device damage.
Attempting to drive a high capacitance digital data bus.
The more capacitance the output drivers have to charge for
each conversion, the more instantaneous digital current is re-
quired from DV
spikes can couple into the analog section, degrading dynamic
performance. Buffering the digital data outputs (with a
74AC541, for example) may be necessary if the data bus to
be driven is heavily loaded. Dynamic performance can also
be improved by adding 47Ω series resistors at each digital
output, reducing the energy coupled back into the converter
output pins.
Using an inadequate amplifier to drive the analog input.
As explained in Section 1.0, the ADC input is a switched ca-
pacitor one and there are voltage spikes present there. This
type if input is more difficult to drive than is a fixed capaci-
tance, and should be considered when choosing a driving
DD
and DGND. These large charging current
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