LTC1094ACN Linear Technology, LTC1094ACN Datasheet - Page 19

• Manufacturer Part Number: LTC1094ACN
• Description: IC DATA ACQ SYS 10BIT 8CH 20-DIP
• Manufacturer: Linear Technology
• Type: Data Acquisition System (DAS), ADCr

Specifications of LTC1094ACN

• Resolution (bits): 10 b
• Data Interface: Serial
• Voltage Supply Source: Dual ±
• Voltage - Supply: 4.5 V ~ 10 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 20-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Sampling Rate (per Second): -

A
Interfacing to the Parallel Port of the
Intel 8051 Family
The Intel 8051 has been chosen to demonstrate the
interface between the LTC1091 and parallel port micro-
processors. Normally, the CS, SCLK and D
would be generated on three port lines and the D
read on a 4th port line. This works very well. However, we
will demonstrate here an interface with the D
of the LTC1091 tied together as described in section 4.
This saves one wire.
The 8051 first sends the start bit and MUX address to the
LTC1091 over the data line connected to P1.2. Then P1.2
is reconfigured as an input (by writing to it a one) and the
8051 reads back the 10-bit A/D result over the same data
line.
DATA (D
ANALOG
INPUTS
PPLICATI
IN
/D
OUT
CLK
CS
D
)
OUT
R2
R3
LTC1091
AND BEFORE THE 4TH FALLING CLK
INPUT AFTER THE 4TH RISING CLK
from LTC1091 Stored in 8051 RAM
8051 P1.2 RECONFIGURED AS AN
MSB
O
B9
B1
U
START
8051 P1.2 OUTPUTS
LSB
D OUT
B8
DATA TO LTC1091
B0
CLK
D IN
S
CS
1
B7
0
I FOR ATIO
U
SGL/
DIFF
B6
MUX ADDRESS
A/D RESULT
0
2
B5
0
ODD/
SIGN
B4
3
0
W
INTO LTC1091
MSBF BIT
LATCHED
MSBF
B3
0
P1.4
P1.3
P1.2
4
B2
0
IN
8051
1091-4 AI17
IN
OUT
and D
U
LTC1091 TAKES CONTROL OF DATA LINE
ON 4TH FALLING CLK
signals
signal
B9
OUT
B8
LABEL
LOOP 1 RLC
LOOP
B7
LTC1091 SENDS A/D RESULT
MNEMONIC OPERAND
MOV
SETB
CLR
MOV
CLR
MOV
SETB
DJNZ
MOV
CLR
MOV
MOV
RLC
SETB
CLR
DJNZ
MOV
MOV
SETB
CLR
CLR
RLC
MOV
RRC
RRC
MOV
SETB
B6
BACK TO 8051 P1.2
B5
A, #FFH
R4, #04
P1.2, C
P1, #04
R4, #09
C, P1.2
R2, A
C, P1.2
C, P1.2
R3, A
P1.4
P1.4
A
P1.3
P1.3
R4, LOOP 1 Next Bit
P1.3
A
P1.3
P1.3
R4, LOOP
P1.3
P1.3
A
A
A
A
P1.4
B4
LTC1093/LTC1094
LTC1091/LTC1092
B3
COMMENTS
D
Make Sure CS Is High
CS Goes Low
Load Counter
Rotate D
SCLK Goes Low
Output D
SCLK Goes High
Bit 2 Becomes an Input
SCLK Goes Low
Load Counter
Read Data Bit into Carry
Rotate Data Bit into Acc
SCLK Goes High
SCLK Goes Low
Next Bit
Store MSBs in R2
Read Data Bit into Carry
SCLK Goes High
SCLK Goes Low
Clear Acc
Rotate Data Bit from Carry to Acc
Read Data Bit into Carry
Rotate Right into Acc
Rotate Right into Acc
Store LSBs in R3
CS Goes High
IN
Word for LTC1091
B2
IN
IN
Bit into Carry
Bit to LTC1091
B1
B0
19
1091/2/3/4 AI18