X9C503S Intersil, X9C503S Datasheet - Page 10
![IC DIGITAL POT 50K 100TP 8SOIC](/photos/6/65/66588/x9c503s_sml.jpg)
X9C503S
Manufacturer Part Number
X9C503S
Description
IC DIGITAL POT 50K 100TP 8SOIC
Manufacturer
Intersil
Series
XDCP™r
Datasheet
1.X9C503SIZT1.pdf
(10 pages)
Specifications of X9C503S
Taps
100
Resistance (ohms)
50K
Number Of Circuits
1
Temperature Coefficient
300 ppm/°C Typical
Memory Type
Non-Volatile
Interface
Up/Down (3-Wire)
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Resistance In Ohms
50K
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
X9C503S8IZ
Manufacturer:
Intersil
Quantity:
50
Part Number:
X9C503S8IZT1
Manufacturer:
INTERSIL
Quantity:
20 000
Company:
Part Number:
X9C503SI
Manufacturer:
XICOR
Quantity:
1 831
Part Number:
X9C503SI
Manufacturer:
INTELSIL
Quantity:
20 000
Company:
Part Number:
X9C503SIZ
Manufacturer:
Intersil
Quantity:
100
Part Number:
X9C503SIZ
Manufacturer:
INTERSIL
Quantity:
20 000
Company:
Part Number:
X9C503SIZT1
Manufacturer:
Intersil
Quantity:
2 500
Company:
Part Number:
X9C503SIZT1
Manufacturer:
Intersil
Quantity:
4 000
Part Number:
X9C503SIZT1
Manufacturer:
INTERSIL
Quantity:
20 000
Plastic Dual-In-Line Packages (PDIP)
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
NOTES:
1. Plastic or metal protrusions of 0.010” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.
4. Dimension eB is measured with the lead tips unconstrained.
5. 8 and 16 lead packages have half end-leads as shown.
SEATING
PLANE
SYMBOL
A1
A2
E1
eA
eB
b2
A
D
E
N
b
c
e
L
L
L
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
e
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
PDIP8
0.210
0.015
0.130
0.018
0.060
0.010
0.375
0.310
0.250
0.100
0.300
0.345
0.125
For information regarding Intersil Corporation and its products, see www.intersil.com
8
D
10
PDIP14
0.210
0.015
0.130
0.018
0.060
0.010
0.750
0.310
0.250
0.100
0.300
0.345
0.125
14
b
X9C102, X9C103, X9C104, X9C503
NOTE 5
A1
A2
A
INCHES
PDIP16
0.210
0.015
0.130
0.018
0.060
0.010
0.750
0.310
0.250
0.100
0.300
0.345
0.125
16
c
PDIP18
0.210
0.015
0.130
0.018
0.060
0.010
0.890
0.310
0.250
0.100
0.300
0.345
0.125
18
eA
eB
E
PDIP20
0.210
0.015
0.130
0.018
0.060
0.010
1.020
0.310
0.250
0.100
0.300
0.345
0.125
20
E1
TOLERANCE
+0.010/-0.015
+0.004/-0.002
+0.015/-0.010
Reference
±0.005
±0.002
±0.010
±0.005
±0.025
±0.010
Basic
Basic
MAX
MIN
N
1
PIN #1
INDEX
2
b2
NOTES
Rev. C 2/07
July 20, 2009
1
2
FN8222.3
N/2