AD5204BRZ100 Analog Devices Inc, AD5204BRZ100 Datasheet - Page 10

• Manufacturer Part Number: AD5204BRZ100
• Description: IC DGTL POT QUAD 100K 24-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD5204BRZ100

• Temperature Coefficient: 700 ppm/°C Typical
• Taps: 256
• Resistance (ohms): 100K
• Number Of Circuits: 4
• Memory Type: Volatile
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V, ±2.3 V ~ 2.7 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Resistance In Ohms: 100K
• End To End Resistance: 100kohm
• No. Of Steps: 256
• Resistance Tolerance: ± 30%
• Supply Voltage Range: 2.7V To 5.5V
• Control Interface: Serial, 3-Wire
• No. Of Pots: Quad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5204/AD5206
The target RDAC latch is loaded with the last eight bits of the
serial data word completing one DAC update. Four separate 8-
bit data words must be clocked in to change all four VR settings.
All digital pins are protected with a series input resistor and
parallel Zener ESD structure shown in Figure 20. Applies to
digital pins CS, SDI, SDO, PR, SHDN, CLK
Figure 23. Resistor Position Nonlinearity Error (Rheostat
Operation; R-INL, R-DNL)
Figure 22. Potentiometer Divider Nonlinearity Error Test
Circuit (INL, DNL)
Figure 19. Detail SDO Output Schematic of the AD5204
Figure 21. ESD Protection of Resistor Terminals
SHDN
CLK
SDI
CS
PR
Figure 18. Equivalent Input Control Logic
Figure 20. ESD Protection of Digital Pins
CLK
SDI
CS
REGISTER
AD5204/AD5206
SERIAL
V+
A, B, W
NO CONNECT
340k
A
DUT
B
A
B
DUT
V
D
W
CK RS
V
SS
W
SS
Q
REGISTER
DECODE
SERIAL
ADDR
V
V+ = V
1LSB = V+/256
LOGIC
MS
V
MS
I
W
DD
RDAC 1
RDAC 2
RDAC 4/6
SDO
GND
–10–
Figure 27. Noninverting Programmable Gain Test Circuit
Figure 25. Power Supply Sensitivity Test Circuit (PSS,
PSRR)
V+
Figure 26. Inverting Programmable Gain Test Circuit
Figure 29. Incremental ON Resistance Test Circuit
I
MS
V+
OFFSET
Figure 28. Gain vs. Frequency Test Circuit
A
DUT
B
Figure 24. Wiper Resistance Test Circuit
~
OFFSET
GND
W
OFFSET
V
GND
DD
GND
V
V
IN
W
V
A
A
B
V
I
DUT
MS
W
B
W
V
=
IN
W
OFFSET BIAS
V
DUT
1V/R
IN
A
2.5V
V
OFFSET BIAS
MS
A
NOMINAL
DUT
I
A
B
SW
W
DUT
V
W
W
B
SS
CODE = ØØ
R
SW
TO V
PSRR (dB) = 20 LOG
PSS (%/%) = –––––––
V+ = V
V+
R
B
WHERE V
AND V
OP279
+
W
=
OP279
DD
= ––––––––––––––––––––––––––
0.1V
+
I
OP42
+5V
SW
V
DD
V
W2
+5V
+15V
–15V
DD
W 2
H
± 10%
+
W1
= V
–[V
0.1V
= V
MS
W1
V
V
MS
DD
MS
WHEN I
I
+ I
W
%
%
V
WHEN I
OUT
V
W
(
OUT
(R
–––––
V
W
V
V
AW
OUT
MS
DD
= 1/R
W
II R
)
= 0
REV. 0
BW
)]