AD5204BRZ100 Analog Devices Inc, AD5204BRZ100 Datasheet - Page 9

• Manufacturer Part Number: AD5204BRZ100
• Description: IC DGTL POT QUAD 100K 24-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD5204BRZ100

• Temperature Coefficient: 700 ppm/°C Typical
• Taps: 256
• Resistance (ohms): 100K
• Number Of Circuits: 4
• Memory Type: Volatile
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V, ±2.3 V ~ 2.7 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Resistance In Ohms: 100K
• End To End Resistance: 100kohm
• No. Of Steps: 256
• Resistance Tolerance: ± 30%
• Supply Voltage Range: 2.7V To 5.5V
• Control Interface: Serial, 3-Wire
• No. Of Pots: Quad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 0
The typical distribution of R
within 1%. However, device-to-device matching is process lot
dependent, having a 30% variation. The change in R
temperature has a 700 ppm/ C temperature coefficient.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates an output voltage
proportional to the input voltage applied to a given terminal.
For example, connecting A terminal to +5 V and B terminal to
ground produces an output voltage at the wiper which can be
any value starting at zero volts up to 1 LSB less than +5 V. Each
LSB of voltage is equal to the voltage applied across Terminal
AB divided by the 256-position resolution of the potentiometer
divider. The general equation defining the output voltage with
respect to ground for any given input voltage applied to termi-
nals AB is:
Operation of the digital potentiometer in the divider mode results
in more accurate operation over temperature. Here the output
voltage is dependent on the ratio of the internal resistors not the
absolute value, therefore, the drift improves to 15 ppm/ C.
DIGITAL INTERFACING
The AD5204/AD5206 contain a standard three-wire serial input
control interface. The three inputs are clock (CLK), CS and
serial data input (SDI). The positive-edge sensitive CLK input
requires clean transitions to avoid clocking incorrect data into
the serial input register. Standard logic families work well. If
mechanical switches are used for product evaluation they should
be debounced by a flip-flop or other suitable means. Figure 17
shows more detail of the internal digital circuitry. When CS is
taken active low the clock loads data into the serial register on
each positive clock edge, see Table IV. When using a positive
(V
referenced to digital ground (GND).
The serial-data-output (SDO) pin contains an open drain n-
channel FET. This output requires a pull-up resistor in order to
DD
V
(AD5204
(AD5204
ONLY)
) and negative (V
ONLY)
W
SHDN
SDO
CLK
(Dx) = Dx/256 V
SDI
CS
DO
DI
SER
REG
Figure 17. Block Diagram
GND
A2
A1
A0
D7
D0
8
SS
(AD5204 ONLY)
ADDR
) supply voltage, the logic levels are still
DEC
EN
AB
BA
PR
AD5204/AD5206
+ V
from channel-to-channel matches
B
D7
D0
D7
D0
LATCH
LATCH
RDAC
RDAC
#4/#6
#1
R
R
V
A1
W1
B1
A4/A6
W4/W6
B4/B6
BA
DD
with
(3)
–9–
transfer data to the next package’s SDI pin. The pull-up resistor
termination voltage may be larger than the V
AD5204 SDO output device, e.g., the AD5204 could operate at
V
could be set at +5 V. This allows for daisy chaining several
RDACs from a single processor serial-data line. Clock period
needs to be increased when using a pull-up resistor to the SDI
pin of the following device in the series. Capacitive loading at
the daisy chain node SDO-SDI between devices must be ac-
counted for to successfully transfer data. When daisy chaining is
used, the CS should be kept low until all the bits of every pack-
age are clocked into their respective serial registers insuring that
the address bits and data bits are in the proper decoding loca-
tion. This would require 22 bits of address and data complying
to the word format provided in Table I if two AD5204 four-
channel RDACs are daisy chained. During shutdown (SHDN)
the SDO output pin is forced to the off (logic high state) to
disable power dissipation in the pull-up resistor. See Figure 19
for equivalent SDO output circuit schematic.
CLK CS PR SHDN Register Activity
L
P
X
X
X
X
X
NOTE: P = positive edge, X = don’t care, SR = shift register.
The data setup and data hold times in the specification table
determine the data valid time requirements. The last 11 bits of
the data word entered into the serial register are held when CS
returns high. At the same time CS goes high it gates the address
decoder enabling one of four or six positive edge triggered RDAC
latches, see Figure 18 detail.
DD
= 3.3 V and the pull-up for interface to the next device
A2
0
0
0
0
1
1
L
L
P
H
X
H
H
Table IV. Input Logic Control Truth Table
H
H
H
H
L
P
H
A1
0
0
1
1
0
0
Table V. Address Decode Table
H
H
H
H
H
H
L
A0
0
1
0
1
0
1
No SR effect, enables SDO pin.
Shift one bit in from the SDI pin.
The eleventh previously entered bit
is shifted out of the SDO pin.
Load SR data into RDAC latch based
on A2, A1, A0 decode (Table V).
No Operation.
Sets all RDAC latches to midscale,
wiper centered and SDO latch
cleared.
Latches all RDAC latches to 80
Open circuits all Resistor A termi-
nals, connects W to B, turns off
SDO output transistor.
Latch Decoded
RDAC#1
RDAC#2
RDAC#3
RDAC#4
RDAC#5 AD5206 Only
RDAC#6 AD5206 Only
AD5204/AD5206
DD
supply of the
H
.