ISL22512WFB8Z Intersil, ISL22512WFB8Z Datasheet - Page 11

• Manufacturer Part Number: ISL22512WFB8Z
• Description: IC POT DGTL PB 16TP LN LP 8-SOIC
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of ISL22512WFB8Z

• Taps: 16
• Resistance (ohms): 10K
• Number Of Circuits: 1
• Temperature Coefficient: 80 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: Pushbutton
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Resistance In Ohms: 10K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
NX (b)
5
SECTION "C-C"
0.10 MIN
PIN #1 ID
INDEX AREA
SEATING PLANE
2X
(DATUM A)
0.05 MIN
2X
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
6
0.05 C
0.10 C
0.10 C
N
(A1)
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
0.10 C
N-1
1
For information regarding Intersil Corporation and its products, see www.intersil.com
N
BOTTOM VIEW
(ND-1) X e
2
A
SIDE VIEW
TOP VIEW
e
3
1
FOR ODD TERMINAL/SIDE
C C
A1
DETAIL “A” PIN 1 ID
11
2
D
e
b
C L
NX L
NX b
0.10 M C A B
0.05 M C
(DATUM B)
5
A
TERMINAL TIP
B
E
4xk
L
C
L
ISL22512
L10.2.1x1.6A
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC
PACKAGE
NOTES:
10. For additional information, to assist with the PCB Land Pattern
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on D and E side,
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
6. The configuration of the pin #1 identifier is optional, but must be
7. Maximum package warpage is 0.05mm.
8. Maximum allowable burrs is 0.076mm in all directions.
9. Same as JEDEC MO-255UABD except:
SYMBOL
respectively.
between 0.15mm and 0.30mm from the terminal tip.
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
No lead-pull-back, "A" MIN dimension = 0.45 not 0.50mm
"L" MAX dimension = 0.45 not 0.42mm.
Design effort, see Intersil Technical Brief TB389.
A1
A3
Nd
Ne
A
D
E
N
b
e
k
L
θ
0.275
0.45
0.15
2.05
1.55
0.20
0.35
MIN
0
-
0.50
LAND PATTERN 10
MILLIMETERS
2.50
1.75
0.127 REF
NOMINAL
0.50 BSC
0.50
0.20
2.10
1.60
0.40
10
4
1
0.25
-
-
-
0.80
0.55
0.05
0.25
2.15
1.65
0.45
MAX
2.00
12
-
March 24, 2008
Rev. 3 6/06
NOTES
FN6679.0
5
2
3
3
4
-
-
-
-
-
-
-
-