ISL23711UIU10Z-T Intersil, ISL23711UIU10Z-T Datasheet - Page 7

• Manufacturer Part Number: ISL23711UIU10Z-T
• Description: IC POT DIGITAL CONTROL 10-MSOP
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of ISL23711UIU10Z-T

• Taps: 128
• Resistance (ohms): 50K
• Number Of Circuits: 1
• Temperature Coefficient: 50 ppm/°C Typical
• Memory Type: Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Resistance In Ohms: 50K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL23711UIU10Z-TTR

of 127 individual resistors connected in series. At either end
of the array and between each resistor is an electronic
switch that transfers the potential at that point to the wiper.
The wiper, when at either fixed terminal, acts like its
mechanical equivalent and does not move beyond the last
position. That is, the counter does not wrap around when
clocked to either extreme.
The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions.
DCP Description
The DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of the
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (R
intermediate nodes, and is equivalent to the wiper terminal
of a mechanical potentiometer. The position of the wiper
terminal is controlled by a 7-bit volatile Wiper Register (WR).
When the WR contains all zeroes (00h), the wiper terminal
(R
contains all ones (7Fh), the wiper terminal (R
its “High” terminal (R
from all zeroes (0 decimal) to all ones (127 decimal), the
wiper moves monotonically from the position closest to R
the position closest to R
between R
resistance between R
While the ISL23711 is being powered up, the WR is reset to
20h (64 decimal), which locates the R
between R
The WR can be read or written directly using the I
interface as described in the following sections.
Memory Description
• A read operation to address 0 outputs the value of the
• A write operation to address 0 only writes to the volatile WR.
I
The ISL23711 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL23711
operates as a slave device in all applications.
All communication over the I
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL LOW
periods. SDA state changes during SCL HIGH are reserved for
2
W
volatile WR.
C Serial Interface
) is closest to its “Low” terminal (R
W
L
and R
and R
H
H
and R
L
.
H
increases monotonically, while the
H
). As the value of the WR increases
and R
H
L
. At the same time, the resistance
pins). The R
2
C interface is conducted by
W
7
decreases monotonically.
W
L
W
). When the WR
at the center
pin is connected to
W
) is closest to
2
C serial
L
to
ISL23711
indicating START and STOP conditions (See Figure 1). On
power-up of the ISL23711 the SDA pin is in the input mode.
All I
which is a HIGH to LOW transition of SDA while SCL is HIGH.
The ISL23711 continuously monitors the SDA and SCL lines for
the START condition and does not respond to any command
until this condition is met (See Figure 1).
All I
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (See Figure 1). A STOP condition at the end of
a read operation, or at the end of a write operation to volatile
bytes only places the device in its standby mode.
An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (See Figure 2).
The ISL23711 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL23711 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation
A valid Identification Byte contains 01010 as the five MSBs,
and the following two bits matching the logic values present
at pins A1, and A0. The LSB is in the Read/Write bit. Its
value is “1” for a Read operation, and “0” for a Write
operation. (See Table 1.)
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL23711 responds with an ACK.
Read Operation
A Read operation is initiated by a master using the following
sequence: a START, the Identification byte (slave address)
with the R/W bit set to “1”. At the moment of the first
acknowledge by the ISL23711 (slave device), the master-
transmitter becomes a master receiver and receives the data
byte from the slave-transmitter.The Master receives the data
byte and issues a non-acknowledge (SDA is HIGH), then a
STOP to terminate the read operation. Since the ISL 23711
has just one WR, it will transmit only one byte (see Figure 4).
2
2
(MSB)
C interface operations must begin with a START condition,
C interface operations must be terminated by a STOP
0
TABLE 1. IDENTIFICATION BYTE FORMAT
1
0
Logic values at pins A1, and A0 respectively
1
0
A1
A0
August 16, 2005
(LSB)
R/W
FN6127.0